SQDMLSLT (indexed)

Signed saturating doubling multiply-subtract by indexed element (top)

This instruction multiplies the odd-numbered signed elements within each 128-bit segment of the first source vector by the specified signed element in the corresponding second source vector segment, and then doubles the result. Each intermediate value is saturated to the double-width N-bit value's signed integer range -2(N-1) to (2(N-1))-1 and is then destructively subtracted from the overlapping double-width elements of the addend and destination vector. Each destination element is saturated to the double-width N-bit element's signed integer range -2(N-1) to (2(N-1))-1.

The elements within the second source vector are specified using an immediate index that selects the same element position within each 128-bit vector segment. The index range is from 0 to one less than the number of elements per 128-bit segment.

It has encodings from 2 classes: 32-bit and 64-bit

32-bit
(FEAT_SVE2 || FEAT_SME)

313029282726252423222120191817161514131211109876543210
01000100101i3hZm0011i3l1ZnZda
sizeST

Encoding

SQDMLSLT <Zda>.S, <Zn>.H, <Zm>.H[<imm>]

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 16; let index : integer = UInt(i3h::i3l); let n : integer = UInt(Zn); let m : integer = UInt(Zm); let da : integer = UInt(Zda); let sel : integer = 1;

64-bit
(FEAT_SVE2 || FEAT_SME)

313029282726252423222120191817161514131211109876543210
01000100111i2hZm0011i2l1ZnZda
sizeST

Encoding

SQDMLSLT <Zda>.D, <Zn>.S, <Zm>.S[<imm>]

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 32; let index : integer = UInt(i2h::i2l); let n : integer = UInt(Zn); let m : integer = UInt(Zm); let da : integer = UInt(Zda); let sel : integer = 1;

Assembler Symbols

<Zda>

Is the name of the third source and destination scalable vector register, encoded in the "Zda" field.

<Zn>

Is the name of the first source scalable vector register, encoded in the "Zn" field.

<Zm>

For the "32-bit" variant: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.

For the "64-bit" variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.

<imm>

For the "32-bit" variant: is the element index, in the range 0 to 7, encoded in the "i3h:i3l" fields.

For the "64-bit" variant: is the element index, in the range 0 to 3, encoded in the "i2h:i2l" fields.

Operation

CheckSVEEnabled(); let VL : integer{} = CurrentVL(); let elements : integer = VL DIV (2 * esize); let eltspersegment : integer = 128 DIV (2 * esize); let operand1 : bits(VL) = Z{}(n); let operand2 : bits(VL) = Z{}(m); var result : bits(VL) = Z{}(da); for e = 0 to elements-1 do let s : integer = e - (e MOD eltspersegment); let element1 : integer = SInt(operand1[(2 * e + sel)*:esize]); let element2 : integer = SInt(operand2[(2 * s + index)*:esize]); let element3 : integer = SInt(result[e*:(2*esize)]); let product : integer = SInt(SignedSat{2*esize}(2 * element1 * element2)); let res : integer = element3 - product; result[e*:(2*esize)] = SignedSat{2*esize}(res); end; Z{VL}(da) = result;

Operational information

This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is CONSTRAINED UNPREDICTABLE:


2026-03_rel 2026-03-26 20:48:11

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