Signed saturating doubling multiply returning high half (by element)
This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.
The results are truncated. For rounded results, see SQRDMULH.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
It has encodings from 2 classes: Scalar and Vector
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | size | L | M | Rm | 1 | 1 | 0 | 0 | H | 0 | Rn | Rd | ||||||||||||
| U | op | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end; let idxdsize : integer{} = 64 << UInt(H); var index : integer; var Rmhi : bit; case size of when '01' => index = UInt(H::L::M); Rmhi = '0'; when '10' => index = UInt(H::L); Rmhi = M; otherwise => EndOfDecode(Decode_UNDEF); end; let d : integer = UInt(Rd); let n : integer = UInt(Rn); let m : integer = UInt(Rmhi::Rm); let esize : integer{} = 8 << UInt(size); let datasize : integer{} = esize; let elements : integer = 1; let round : boolean = FALSE;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | Q | 0 | 0 | 1 | 1 | 1 | 1 | size | L | M | Rm | 1 | 1 | 0 | 0 | H | 0 | Rn | Rd | ||||||||||||
| U | op | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end; let idxdsize : integer{} = 64 << UInt(H); var index : integer; var Rmhi : bit; case size of when '01' => index = UInt(H::L::M); Rmhi = '0'; when '10' => index = UInt(H::L); Rmhi = M; otherwise => EndOfDecode(Decode_UNDEF); end; let d : integer = UInt(Rd); let n : integer = UInt(Rn); let m : integer = UInt(Rmhi::Rm); let esize : integer{} = 8 << UInt(size); let datasize : integer{} = 64 << UInt(Q); let elements : integer = datasize DIV esize; let round : boolean = FALSE;
| <V> |
Is a width specifier,
encoded in
|
| <d> |
Is the number of the SIMD&FP destination register, encoded in the "Rd" field. |
| <n> |
Is the number of the first SIMD&FP source register, encoded in the "Rn" field. |
| <Ts> |
Is an element size specifier,
encoded in
|
| <index> |
Is the element index,
encoded in
|
| <Vd> |
Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
| <T> |
Is an arrangement specifier,
encoded in
|
| <Vn> |
Is the name of the first SIMD&FP source register, encoded in the "Rn" field. |
AArch64_CheckFPAdvSIMDEnabled(); let operand1 : bits(datasize) = V{}(n); let operand2 : bits(idxdsize) = V{}(m); var result : bits(datasize); var element1 : integer; var element2 : integer; var product : integer; var sat : boolean; element2 = SInt(operand2[index*:esize]); for e = 0 to elements-1 do element1 = SInt(operand1[e*:esize]); product = 2 * element1 * element2; product = RShr(product, esize, round); // The following only saturates if element1 and element2 equal -(2^(esize-1)) (result[e*:esize], sat) = SignedSatQ{esize}(product); if sat then FPSR().QC = '1'; end; end; V{datasize}(d) = result;
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
2026-03_rel 2026-03-26 20:48:11
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