Saturating rounding doubling complex integer multiply-add high by indexed element
This instruction multiplies without saturation the duplicated real components for rotations 0 and 180, or imaginary components for rotations 90 and 270, of the integral numbers in each 128-bit segment of the first source vector by the specified complex number in the corresponding the second source vector segment rotated by 0, 90, 180 or 270 degrees in the direction from the positive real axis towards the positive imaginary axis, when considered in polar representation.
This instruction then doubles and adds the products to the corresponding components of the complex numbers in the addend vector, and destructively places the most significant rounded half of the results in the corresponding elements of the addend vector. Each result element is saturated to the N-bit element's signed integer range -2(N-1) to (2(N-1))-1. This instruction is unpredicated.
These transformations permit the creation of a variety of multiply-add and multiply-subtract operations on complex numbers by combining two of these instructions with the same vector operands but with rotations that are 90 degrees apart.
Each complex number is represented in a vector register as an even/odd pair of elements with the real part in the even-numbered element and the imaginary part in the odd-numbered element.
It has encodings from 2 classes: 16-bit and 32-bit
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | i2 | Zm | 0 | 1 | 1 | 1 | rot | Zn | Zda | ||||||||||||
| size | |||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 16; let index : integer = UInt(i2); let n : integer = UInt(Zn); let m : integer = UInt(Zm); let da : integer = UInt(Zda); let sel_a : integer = UInt(rot[0]); let sel_b : integer = UInt(NOT(rot[0])); let sub_r : boolean = (rot[0] != rot[1]); let sub_i : boolean = (rot[1] == '1');
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | i1 | Zm | 0 | 1 | 1 | 1 | rot | Zn | Zda | ||||||||||||
| size | |||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 32; let index : integer = UInt(i1); let n : integer = UInt(Zn); let m : integer = UInt(Zm); let da : integer = UInt(Zda); let sel_a : integer = UInt(rot[0]); let sel_b : integer = UInt(NOT(rot[0])); let sub_r : boolean = (rot[0] != rot[1]); let sub_i : boolean = (rot[1] == '1');
| <Zda> |
Is the name of the third source and destination scalable vector register, encoded in the "Zda" field. |
| <Zn> |
Is the name of the first source scalable vector register, encoded in the "Zn" field. |
| <imm> |
For the "16-bit" variant: is the element index, in the range 0 to 3, encoded in the "i2" field. |
|
For the "32-bit" variant: is the element index, in the range 0 to 1, encoded in the "i1" field. |
| <const> |
Is the const specifier,
encoded in
|
CheckSVEEnabled(); let VL : integer{} = CurrentVL(); let pairs : integer = VL DIV (2 * esize); let pairspersegment : integer = 128 DIV (2 * esize); let operand1 : bits(VL) = Z{}(n); let operand2 : bits(VL) = Z{}(m); let operand3 : bits(VL) = Z{}(da); var result : bits(VL); var res_r, res_i : integer; for p = 0 to pairs-1 do let segmentbase : integer = p - (p MOD pairspersegment); let s : integer = segmentbase + index; let elt1_a : integer = SInt(operand1[(2 * p + sel_a)*:esize]); let elt2_a : integer = SInt(operand2[(2 * s + sel_a)*:esize]); let elt2_b : integer = SInt(operand2[(2 * s + sel_b)*:esize]); let elt3_r : bits(esize) = operand3[(2 * p + 0)*:esize]; let elt3_i : bits(esize) = operand3[(2 * p + 1)*:esize]; let product_r : integer = elt1_a * elt2_a; let product_i : integer = elt1_a * elt2_b; if sub_r then res_r = (SInt(elt3_r) << esize) - 2 * product_r; else res_r = (SInt(elt3_r) << esize) + 2 * product_r; end; res_r = (res_r + (1 << (esize-1))) >> esize; result[(2 * p + 0)*:esize] = SignedSat{esize}(res_r); if sub_i then res_i = (SInt(elt3_i) << esize) - 2 * product_i; else res_i = (SInt(elt3_i) << esize) + 2 * product_i; end; res_i = (res_i + (1 << (esize-1))) >> esize; result[(2 * p + 1)*:esize] = SignedSat{esize}(res_i); end; Z{VL}(da) = result;
This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is CONSTRAINED UNPREDICTABLE:
2026-03_rel 2026-03-26 20:48:11
Copyright © 2010-2026 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.