SQRDMLSH (by element)

Signed saturating rounding doubling multiply subtract returning high half (by element)

This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.

If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

It has encodings from 2 classes: Scalar and Vector

Scalar
(FEAT_RDM)

313029282726252423222120191817161514131211109876543210
01111111sizeLMRm1111H0RnRd
US

Encoding

SQRDMLSH <V><d>, <V><n>, V<m>.<Ts>[<index>]

Decode for this encoding

if !IsFeatureImplemented(FEAT_RDM) then EndOfDecode(Decode_UNDEF); end; let idxdsize : integer{} = 64 << UInt(H); var index : integer; var Rmhi : bit; case size of when '01' => index = UInt(H::L::M); Rmhi = '0'; when '10' => index = UInt(H::L); Rmhi = M; otherwise => EndOfDecode(Decode_UNDEF); end; let d : integer = UInt(Rd); let n : integer = UInt(Rn); let m : integer = UInt(Rmhi::Rm); let esize : integer{} = 8 << UInt(size); let datasize : integer{} = esize; let elements : integer = 1; let rounding : boolean = TRUE;

Vector
(FEAT_RDM)

313029282726252423222120191817161514131211109876543210
0Q101111sizeLMRm1111H0RnRd
US

Encoding

SQRDMLSH <Vd>.<T>, <Vn>.<T>, V<m>.<Ts>[<index>]

Decode for this encoding

if !IsFeatureImplemented(FEAT_RDM) then EndOfDecode(Decode_UNDEF); end; let idxdsize : integer{} = 64 << UInt(H); var index : integer; var Rmhi : bit; case size of when '01' => index = UInt(H::L::M); Rmhi = '0'; when '10' => index = UInt(H::L); Rmhi = M; otherwise => EndOfDecode(Decode_UNDEF); end; let d : integer = UInt(Rd); let n : integer = UInt(Rn); let m : integer = UInt(Rmhi::Rm); let esize : integer{} = 8 << UInt(size); let datasize : integer{} = 64 << UInt(Q); let elements : integer = datasize DIV esize; let rounding : boolean = TRUE;

Assembler Symbols

<V>

Is a width specifier, encoded in size:

size <V>
00 RESERVED
01 H
10 S
11 RESERVED
<d>

Is the number of the SIMD&FP destination register, encoded in the "Rd" field.

<n>

Is the number of the first SIMD&FP source register, encoded in the "Rn" field.

<m>

Is the number of the second SIMD&FP source register, encoded in (size :: M :: Rm):

size <m>
00 RESERVED
01 UInt('0' :: Rm)
10 UInt(M :: Rm)
11 RESERVED
Restricted to 0-15 when element size <Ts> is H.
<Ts>

Is an element size specifier, encoded in size:

size <Ts>
00 RESERVED
01 H
10 S
11 RESERVED
<index>

Is the element index, encoded in (size :: H :: L :: M):

size <index>
00 RESERVED
01 UInt(H :: L :: M)
10 UInt(H :: L)
11 RESERVED
<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T>

Is an arrangement specifier, encoded in (size :: Q):

size Q <T>
00 x RESERVED
01 0 4H
01 1 8H
10 0 2S
10 1 4S
11 x RESERVED
<Vn>

Is the name of the first SIMD&FP source register, encoded in the "Rn" field.

Operation

AArch64_CheckFPAdvSIMDEnabled(); let operand1 : bits(datasize) = V{}(n); let operand2 : bits(idxdsize) = V{}(m); let operand3 : bits(datasize) = V{}(d); var result : bits(datasize); var element1 : integer; var element2 : integer; var element3 : integer; var accum : integer; var sat : boolean; element2 = SInt(operand2[index*:esize]); for e = 0 to elements-1 do element1 = SInt(operand1[e*:esize]); element3 = SInt(operand3[e*:esize]); accum = (element3 << esize) - 2 * (element1 * element2); accum = RShr(accum, esize, rounding); (result[e*:esize], sat) = SignedSatQ{esize}(accum); if sat then FPSR().QC = '1'; end; end; V{datasize}(d) = result;


2026-03_rel 2026-03-26 20:48:11

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