Signed saturating extract narrow
This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.
If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.
The SQXTN instruction writes the vector to the lower half of the destination register and clears the upper half. The SQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
It has encodings from 2 classes: Scalar and Vector
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | size | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | Rn | Rd | |||||||||
| U | opcode | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end; if size == '11' then EndOfDecode(Decode_UNDEF); end; let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let esize : integer{} = 8 << UInt(size); let datasize : integer{} = esize; let part : integer = 0; let elements : integer = 1; let unsigned : boolean = FALSE;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | Q | 0 | 0 | 1 | 1 | 1 | 0 | size | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | Rn | Rd | |||||||||
| U | opcode | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end; if size == '11' then EndOfDecode(Decode_UNDEF); end; let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let esize : integer{} = 8 << UInt(size); let datasize : integer{} = 64; let part : integer = UInt(Q); let elements : integer = datasize DIV esize; let unsigned : boolean = FALSE;
| <Vb> |
Is the destination width specifier,
encoded in
|
| <d> |
Is the number of the SIMD&FP destination register, encoded in the "Rd" field. |
| <Va> |
Is the source width specifier,
encoded in
|
| <n> |
Is the number of the SIMD&FP source register, encoded in the "Rn" field. |
| <Vd> |
Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
| <Tb> |
Is an arrangement specifier,
encoded in
|
| <Vn> |
Is the name of the SIMD&FP source register, encoded in the "Rn" field. |
| <Ta> |
Is an arrangement specifier,
encoded in
|
AArch64_CheckFPAdvSIMDEnabled(); let operand : bits(2*datasize) = V{}(n); var result : bits(datasize); var element : bits(2*esize); var sat : boolean; for e = 0 to elements-1 do element = operand[e*:(2*esize)]; (result[e*:esize], sat) = SatQ{esize}(SInt(element), unsigned); if sat then FPSR().QC = '1'; end; end; Vpart{datasize}(d, part) = result;
2026-03_rel 2026-03-26 20:48:11
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