Signed saturating extract narrow to unsigned integer (bottom)
This instruction saturates the signed integer value in each source element to an unsigned integer value that is half the original source element width, and places the results in the even-numbered half-width destination elements, while setting the odd-numbered elements to zero.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | tszh | 1 | tszl | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | Zn | Zd | |||||||||
| opc | T | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; let tsize : bits(3) = tszh::tszl; if !(tsize IN {'001', '010', '100'}) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 16 << HighestSetBitNZ(tsize); let n : integer = UInt(Zn); let d : integer = UInt(Zd);
| <Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field. |
| <T> |
Is the size specifier,
encoded in
|
| <Zn> |
Is the name of the source scalable vector register, encoded in the "Zn" field. |
| <Tb> |
Is the size specifier,
encoded in
|
CheckSVEEnabled(); let VL : integer{} = CurrentVL(); let elements : integer = VL DIV esize; let operand1 : bits(VL) = Z{}(n); var result : bits(VL); let halfesize : integer{} = esize DIV 2; for e = 0 to elements-1 do let element1 : integer = SInt(operand1[e*:esize]); let res : bits(halfesize) = UnsignedSat{halfesize}(element1); result[(2*e + 0)*:halfesize] = res; result[(2*e + 1)*:halfesize] = Zeros{halfesize}; end; Z{VL}(d) = result;
2026-03_rel 2026-03-26 20:48:11
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