SRI

Shift right and insert (immediate)

This instruction shifts each source vector element right by an immediate value, and inserts the result into the corresponding vector element in the destination vector register, merging the shifted bits from each source element with existing bits in each destination vector element. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. This instruction is unpredicated.

SVE2
(FEAT_SVE2 || FEAT_SME)

313029282726252423222120191817161514131211109876543210
01000101tszh0tszlimm3111100ZnZd
op

Encoding

SRI <Zd>.<T>, <Zn>.<T>, #<const>

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; let tsize : bits(4) = tszh::tszl; if tsize == '0000' then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8 << HighestSetBitNZ(tsize); let n : integer = UInt(Zn); let d : integer = UInt(Zd); let shift : integer = (2 * esize) - UInt(tsize::imm3);

Assembler Symbols

<Zd>

Is the name of the destination scalable vector register, encoded in the "Zd" field.

<T>

Is the size specifier, encoded in (tszh :: tszl):

tszh tszl <T>
00 00 RESERVED
00 01 B
00 1x H
01 xx S
1x xx D
<Zn>

Is the name of the source scalable vector register, encoded in the "Zn" field.

<const>

Is the immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3".

Operation

CheckSVEEnabled(); let VL : integer{} = CurrentVL(); let elements : integer = VL DIV esize; let operand : bits(VL) = Z{}(n); var result : bits(VL) = Z{}(d); for e = 0 to elements-1 do let element1 : bits(esize) = result[e*:esize]; let element2 : bits(esize) = operand[e*:esize]; let mask : bits(esize) = LSR(Ones{esize}, shift); let shiftedval : bits(esize) = LSR(element2, shift); result[e*:esize] = (element1 AND (NOT mask)) OR shiftedval; end; Z{VL}(d) = result;

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.


2026-03_rel 2026-03-26 20:48:11

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