Signed shift left long (immediate)
This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.
The SSHLL instruction extracts vector elements from the lower half of the source register. The SSHLL2 instruction extracts vector elements from the upper half of the source register.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
This instruction is used by the alias SXTL, SXTL2.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | Q | 0 | 0 | 1 | 1 | 1 | 1 | 0 | != 0000 | immb | 1 | 0 | 1 | 0 | 0 | 1 | Rn | Rd | |||||||||||||
| U | immh | opcode | |||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end; if immh[3] == '1' then EndOfDecode(Decode_UNDEF); end; let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let esize : integer{} = 8 << HighestSetBitNZ(immh[2:0]); let datasize : integer{} = 64; let part : integer = UInt(Q); let elements : integer = datasize DIV esize; let shift : integer = UInt(immh::immb) - esize; let unsigned : boolean = FALSE;
| <Vd> |
Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
| <Ta> |
Is an arrangement specifier,
encoded in
|
| <Vn> |
Is the name of the SIMD&FP source register, encoded in the "Rn" field. |
| <Tb> |
Is an arrangement specifier,
encoded in
|
| <shift> |
Is the left shift amount, in the range 0 to the source element width in bits minus 1,
encoded in
|
| Alias | Is preferred when |
|---|---|
| SXTL, SXTL2 | immb == '000' && BitCount(immh) == 1 |
AArch64_CheckFPAdvSIMDEnabled(); let operand : bits(datasize) = Vpart{}(n, part); var result : bits(datasize*2); for e = 0 to elements-1 do let opelt : bits(esize) = operand[e*:esize]; let element : integer = if unsigned then UInt(opelt) else SInt(opelt); result[e*:(2*esize)] = (element << shift)[2*esize-1:0]; end; V{datasize*2}(d) = result;
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
2026-03_rel 2026-03-26 20:48:11
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