SSHR

Signed shift right (immediate)

This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSHR.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

It has encodings from 2 classes: Scalar and Vector

Scalar
(FEAT_AdvSIMD)

313029282726252423222120191817161514131211109876543210
0101111101xxximmb000001RnRd
Uimmho1o0

Encoding

SSHR D<d>, D<n>, #<shift>

Decode for this encoding

if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end; if immh[3] != '1' then EndOfDecode(Decode_UNDEF); end; let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let esize : integer{} = 8 << 3; let datasize : integer{} = esize; let elements : integer = 1; let shift : integer = (esize * 2) - UInt(immh::immb); let unsigned : boolean = FALSE; let round : boolean = FALSE;

Vector
(FEAT_AdvSIMD)

313029282726252423222120191817161514131211109876543210
0Q0011110!= 0000immb000001RnRd
Uimmho1o0

Encoding

SSHR <Vd>.<T>, <Vn>.<T>, #<shift>

Decode for this encoding

if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end; if immh[3]::Q == '10' then EndOfDecode(Decode_UNDEF); end; let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let esize : integer{} = 8 << HighestSetBitNZ(immh); let datasize : integer{} = 64 << UInt(Q); let elements : integer = datasize DIV esize; let shift : integer = (esize * 2) - UInt(immh::immb); let unsigned : boolean = FALSE; let round : boolean = FALSE;

Assembler Symbols

<d>

Is the number of the SIMD&FP destination register, encoded in the "Rd" field.

<n>

Is the number of the first SIMD&FP source register, encoded in the "Rn" field.

<shift>

For the "Scalar" variant: is the right shift amount, in the range 1 to 64, encoded as 128 - UInt("immh:immb").

For the "Vector" variant: is the right shift amount, in the range 1 to the element width in bits, encoded in (immh :: immb):

immh <shift>
0001 16 - UInt(immh :: immb)
001x 32 - UInt(immh :: immb)
01xx 64 - UInt(immh :: immb)
1xxx 128 - UInt(immh :: immb)
<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T>

Is an arrangement specifier, encoded in (immh :: Q):

immh Q <T>
0001 0 8B
0001 1 16B
001x 0 4H
001x 1 8H
01xx 0 2S
01xx 1 4S
1xxx 0 RESERVED
1xxx 1 2D
<Vn>

Is the name of the SIMD&FP source register, encoded in the "Rn" field.

Operation

AArch64_CheckFPAdvSIMDEnabled(); let operand : bits(datasize) = V{}(n); var result : bits(datasize); var element : integer; for e = 0 to elements-1 do let opelt : bits(esize) = operand[e*:esize]; if unsigned then element = RShr(UInt(opelt), shift, round); else element = RShr(SInt(opelt), shift, round); end; result[e*:esize] = element[esize-1:0]; end; V{datasize}(d) = result;

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.


2026-03_rel 2026-03-26 20:48:11

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