var scale : bits(2) = opcode[2:1]; let selem : integer = UInt(opcode[0]::R) + 1; var replicate : boolean = FALSE; var index : integer; case scale of when '11' => // load and replicate if L == '0' || S == '1' then EndOfDecode(Decode_UNDEF); end; scale = size; replicate = TRUE; when '00' => index = UInt(Q::S::size); // B[0-15] when '01' => if size[0] == '1' then EndOfDecode(Decode_UNDEF); end; index = UInt(Q::S::size[1]); // H[0-7] when '10' => if size[1] == '1' then EndOfDecode(Decode_UNDEF); end; if size[0] == '0' then index = UInt(Q::S); // S[0-3] else if S == '1' then EndOfDecode(Decode_UNDEF); end; index = UInt(Q); // D[0-1] scale = '11'; end; end; let datasize : integer{} = 64 << UInt(Q); let esize : integer{} = 8 << UInt(scale);

AArch64_CheckFPAdvSIMDEnabled(); var address : bits(64); var eaddr : bits(64); var rval : bits(128); var element : bits(esize); var offs : bits(64) = Zeros{64}; let ebytes : integer{} = esize DIV 8; let privileged : boolean = PSTATE.EL != EL0; let accdesc : AccessDescriptor = CreateAccDescASIMD(MemOp_STORE, nontemporal, tagchecked, privileged); if n == 31 then CheckSPAlignment(); address = SP{64}(); else address = X{64}(n); end; if replicate then // load and replicate to all elements for s = 0 to selem-1 do eaddr = AddressIncrement(address, offs, accdesc); element = Mem{esize}(eaddr, accdesc); // replicate to fill 128- or 64-bit register V{datasize}(t) = Replicate{datasize}(element); offs = offs + ebytes; t = (t + 1) MOD 32; end; else // load/store one element per register for s = 0 to selem-1 do rval = V{128}(t); eaddr = AddressIncrement(address, offs, accdesc); // extract from one lane of 128-bit register Mem{esize}(eaddr, accdesc) = rval[index*:esize]; offs = offs + ebytes; t = ( t + 1 ) MOD 32; end; end; if wback then if m != 31 then offs = X{64}(m); end; address = AddressAdd(address, offs, accdesc); if n == 31 then SP{64}() = address; else X{64}(n) = address; end; end;