ST1B (vector plus immediate)

Scatter store bytes from a vector (immediate index)

This instruction performs a scatter store of bytes from the Active elements of a vector register to the memory addresses generated by a vector base plus immediate index. The index is in the range 0 to 31. Inactive elements are not written to memory.

This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.

It has encodings from 2 classes: 32-bit element and 64-bit element

32-bit element
(FEAT_SVE)

313029282726252423222120191817161514131211109876543210
11100100011imm5101PgZnZt
msz

Encoding

ST1B { <Zt>.S }, <Pg>, [<Zn>.S{, #<imm>}]

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF); end; let t : integer = UInt(Zt); let n : integer = UInt(Zn); let g : integer = UInt(Pg); let esize : integer{} = 32; let msize : integer{} = 8; let offset : integer = UInt(imm5);

64-bit element
(FEAT_SVE)

313029282726252423222120191817161514131211109876543210
11100100010imm5101PgZnZt
msz

Encoding

ST1B { <Zt>.D }, <Pg>, [<Zn>.D{, #<imm>}]

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF); end; let t : integer = UInt(Zt); let n : integer = UInt(Zn); let g : integer = UInt(Pg); let esize : integer{} = 64; let msize : integer{} = 8; let offset : integer = UInt(imm5);

Assembler Symbols

<Zt>

Is the name of the scalable vector register to be transferred, encoded in the "Zt" field.

<Pg>

Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Zn>

Is the name of the base scalable vector register, encoded in the "Zn" field.

<imm>

Is the optional unsigned immediate byte offset, in the range 0 to 31, defaulting to 0, encoded in the "imm5" field.

Operation

CheckNonStreamingSVEEnabled(); let VL : integer{} = CurrentVL(); let PL : integer{} = VL DIV 8; let elements : integer = VL DIV esize; let mask : bits(PL) = P{}(g); var base : bits(VL); var src : bits(VL); let mbytes : integer{} = msize DIV 8; let contiguous : boolean = FALSE; let nontemporal : boolean = FALSE; let predicated : boolean = TRUE; let tagchecked : boolean = TRUE; let accdesc : AccessDescriptor = CreateAccDescSVE(MemOp_STORE, nontemporal, contiguous, predicated, tagchecked); if AnyActiveElement{PL}(mask, esize) then base = Z{VL}(n); src = Z{VL}(t); end; for e = 0 to elements-1 do if ActivePredicateElement{PL}(mask, e, esize) then let baddr : bits(64) = ZeroExtend{}(base[e*:esize]); let addr : bits(64) = AddressAdd(baddr, offset * mbytes, accdesc); Mem{msize}(addr, accdesc) = src[e*:esize][msize-1:0]; end; end;

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.


2026-03_rel 2026-03-26 20:48:11

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