Store multiple 4-element structures from four registers
This instruction stores multiple 4-element structures to memory from four SIMD&FP registers, with interleaving. Every element of each register is stored.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
It has encodings from 2 classes: No offset and Post-index
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | Q | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | size | Rn | Rt | |||||||||
| L | opcode | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end; let t : integer = UInt(Rt); let n : integer = UInt(Rn); let m : integer = ARBITRARY : integer; let wback : boolean = FALSE; let nontemporal : boolean = FALSE; let tagchecked : boolean = wback || n != 31;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | Q | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | Rm | 0 | 0 | 0 | 0 | size | Rn | Rt | |||||||||||||
| L | opcode | ||||||||||||||||||||||||||||||
ST4 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <imm>
ST4 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <Xm>
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end; let t : integer = UInt(Rt); let n : integer = UInt(Rn); let m : integer = UInt(Rm); let wback : boolean = TRUE; let nontemporal : boolean = FALSE; let tagchecked : boolean = wback || n != 31;
| <Vt> |
Is the name of the first or only SIMD&FP register to be transferred, encoded in the "Rt" field. |
| <T> |
Is an arrangement specifier,
encoded in
|
| <Vt2> |
Is the name of the second SIMD&FP register to be transferred, encoded as "Rt" plus 1 modulo 32. |
| <Vt3> |
Is the name of the third SIMD&FP register to be transferred, encoded as "Rt" plus 2 modulo 32. |
| <Vt4> |
Is the name of the fourth SIMD&FP register to be transferred, encoded as "Rt" plus 3 modulo 32. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <imm> |
Is the post-index immediate offset,
encoded in
|
| <Xm> |
Is the 64-bit name of the general-purpose post-index register, excluding XZR, encoded in the "Rm" field. |
let datasize : integer{} = 64 << UInt(Q); let esize : integer{} = 8 << UInt(size); let elements : integer = datasize DIV esize; let rpt : integer = 1; let selem : integer = 4; // .1D format only permitted with LD1 & ST1 if size::Q == '110' && selem != 1 then EndOfDecode(Decode_UNDEF); end;
AArch64_CheckFPAdvSIMDEnabled(); var address : bits(64); var eaddr : bits(64); var rval : bits(datasize); var tt : integer; var offs : bits(64) = Zeros{64}; let ebytes : integer{} = esize DIV 8; let privileged : boolean = PSTATE.EL != EL0; let accdesc : AccessDescriptor = CreateAccDescASIMD(MemOp_STORE, nontemporal, tagchecked, privileged); if n == 31 then CheckSPAlignment(); address = SP{64}(); else address = X{64}(n); end; for r = 0 to rpt-1 do for e = 0 to elements-1 do tt = (t + r) MOD 32; for s = 0 to selem-1 do rval = V{datasize}(tt); eaddr = AddressIncrement(address, offs, accdesc); Mem{esize}(eaddr, accdesc) = rval[e*:esize]; offs = offs + ebytes; tt = (tt + 1) MOD 32; end; end; end; if wback then if m != 31 then offs = X{64}(m); end; address = AddressAdd(address, offs, accdesc); if n == 31 then SP{64}() = address; else X{64}(n) = address; end; end;
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
2026-03_rel 2026-03-26 20:48:11
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