STFADD, STFADDL

Atomic floating-point add, without return

This instruction atomically loads a 16-bit, 32-bit, or 64-bit value from memory, performs a floating-point add with the value held in a register, and stores the result back to memory.

This instruction:

For more information about memory ordering semantics, see Load-Acquire, Store-Release.

For information about addressing modes, see Load/Store addressing modes.

Floating-point
(FEAT_LSFE)

313029282726252423222120191817161514131211109876543210
size1111000R1Rs100000Rn11111
VRAo3opcRt

Encoding for the Half-precision no memory ordering variant

Applies when (size == 01 && R == 0)

STFADD <Hs>, [<Xn|SP>]

Encoding for the Half-precision release variant

Applies when (size == 01 && R == 1)

STFADDL <Hs>, [<Xn|SP>]

Encoding for the Single-precision no memory ordering variant

Applies when (size == 10 && R == 0)

STFADD <Ss>, [<Xn|SP>]

Encoding for the Single-precision release variant

Applies when (size == 10 && R == 1)

STFADDL <Ss>, [<Xn|SP>]

Encoding for the Double-precision no memory ordering variant

Applies when (size == 11 && R == 0)

STFADD <Ds>, [<Xn|SP>]

Encoding for the Double-precision release variant

Applies when (size == 11 && R == 1)

STFADDL <Ds>, [<Xn|SP>]

Decode for all variants of this encoding

if !IsFeatureImplemented(FEAT_LSFE) then EndOfDecode(Decode_UNDEF); end; let s : integer = UInt(Rs); let n : integer = UInt(Rn); let datasize : integer{} = 8 << UInt(size); let acquire : boolean = FALSE; let release : boolean = R == '1'; let tagchecked : boolean = n != 31;

Assembler Symbols

<Hs>

Is the 16-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Ss>

Is the 32-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.

<Ds>

Is the 64-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.

Operation

AArch64_CheckFPEnabled(); var address : bits(64); var value : bits(datasize); var data : bits(datasize); let accdesc : AccessDescriptor = CreateAccDescFPAtomicOp(MemAtomicOp_FPADD, acquire, release, tagchecked); value = V{datasize}(s); if n == 31 then CheckSPAlignment(); address = SP{64}(); else address = X{64}(n); end; let comparevalue : bits(datasize) = ARBITRARY : bits(datasize); // Irrelevant when not executing CAS data = MemAtomic{datasize}(address, comparevalue, value, accdesc);


2026-03_rel 2026-03-26 20:48:11

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