Store Allocation Tag and pair of registers
This instruction stores an Allocation Tag and two 64-bit doublewords to memory, from two registers. The address used for the store is calculated from the base register and an immediate signed offset scaled by the Tag Granule. The Allocation Tag is calculated from the Logical Address Tag in the base register.
This instruction generates an Unchecked access.
It has encodings from 3 classes: Post-index , Pre-index and Signed offset
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | simm7 | Rt2 | Rn | Rt | ||||||||||||||||||
| opc | VR | L | |||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_MTE) then EndOfDecode(Decode_UNDEF); end; let t : integer{} = UInt(Rt); let t2 : integer{} = UInt(Rt2); let n : integer{} = UInt(Rn); let offset : bits(64) = LSL(SignExtend{64}(simm7), LOG2_TAG_GRANULE); let writeback : boolean = TRUE; let postindex : boolean = TRUE;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | simm7 | Rt2 | Rn | Rt | ||||||||||||||||||
| opc | VR | L | |||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_MTE) then EndOfDecode(Decode_UNDEF); end; let t : integer{} = UInt(Rt); let t2 : integer{} = UInt(Rt2); let n : integer{} = UInt(Rn); let offset : bits(64) = LSL(SignExtend{64}(simm7), LOG2_TAG_GRANULE); let writeback : boolean = TRUE; let postindex : boolean = FALSE;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | simm7 | Rt2 | Rn | Rt | ||||||||||||||||||
| opc | VR | L | |||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_MTE) then EndOfDecode(Decode_UNDEF); end; let t : integer{} = UInt(Rt); let t2 : integer{} = UInt(Rt2); let n : integer{} = UInt(Rn); let offset : bits(64) = LSL(SignExtend{64}(simm7), LOG2_TAG_GRANULE); let writeback : boolean = FALSE; let postindex : boolean = FALSE;
| <Xt1> |
Is the 64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field. |
| <Xt2> |
Is the 64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
var address : bits(64); if n == 31 then CheckSPAlignment(); address = SP{64}(); else address = X{64}(n); end; let stzgm : boolean = FALSE; let ispair : boolean = TRUE; let accdesc : AccessDescriptor = CreateAccDescLDGSTG(MemOp_STORE, stzgm, ispair, t, t2); if !postindex then address = AddressAdd(address, offset, accdesc); end; if !IsAlignedSize(address, TAG_GRANULE) then let fault : FaultRecord = AlignmentFault(accdesc, address); AArch64_Abort(fault); end; let data : bits(128) = (if BigEndian(accdesc.acctype) then X{64}(t) ::X{64}(t2) else X{64}(t2)::X{64}(t)); Mem{128}(address, accdesc) = data; AArch64_MemTag(address, accdesc) = AArch64_AllocationTagFromAddress(address); if writeback then if postindex then address = AddressAdd(address, offset, accdesc); end; if n == 31 then SP{64}() = address; else X{64}(n) = address; end; end;
2026-03_rel 2026-03-26 20:48:11
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