STLLR -- A64

STLLR

Store LORelease register

This instruction stores a 32-bit word or a 64-bit doubleword to a memory location, from a register. The instruction also has memory ordering semantics as described in Load LOAcquire, Store LORelease. For information about addressing modes, see Load/Store addressing modes.

No offset
(FEAT_LOR)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	x	0	0	1	0	0	0	1	0	0	(1)	(1)	(1)	(1)	(1)	0	(1)	(1)	(1)	(1)	(1)	Rn					Rt
size									L		Rs					o0	Rt2

Encoding for the 32-bit variant

Applies when (size == 10)

STLLR <Wt>, [<Xn|SP>{, #0}]

Encoding for the 64-bit variant

Applies when (size == 11)

STLLR <Xt>, [<Xn|SP>{, #0}]

Decode for all variants of this encoding

if !IsFeatureImplemented(FEAT_LOR) then EndOfDecode(Decode_UNDEF); end; let t : integer{} = UInt(Rt); let n : integer{} = UInt(Rn); let elsize : integer{} = 8 << UInt(size); let acquire : boolean = FALSE; let tagchecked : boolean = n != 31;

Assembler Symbols

<Wt>	Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Xt>	Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

Operation

var address : bits(64); let dbytes : integer{} = elsize DIV 8; let accdesc : AccessDescriptor = CreateAccDescLOR(MemOp_STORE, tagchecked, acquire, t); if n == 31 then CheckSPAlignment(); address = SP{64}(); else address = X{64}(n); end; Mem{elsize}(address, accdesc) = X{elsize}(t);

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.

2026-03_rel 2026-03-26 20:48:11