Store pair of SIMD&FP registers
This instruction stores a pair of SIMD&FP registers to memory. The address used for the store is calculated from a base register value and an immediate offset.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
It has encodings from 3 classes: Post-index , Pre-index and Signed offset
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| opc | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | imm7 | Rt2 | Rn | Rt | |||||||||||||||||||
| VR | L | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_FP) then EndOfDecode(Decode_UNDEF); end; let wback : boolean = TRUE; let postindex : boolean = TRUE;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| opc | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | imm7 | Rt2 | Rn | Rt | |||||||||||||||||||
| VR | L | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_FP) then EndOfDecode(Decode_UNDEF); end; let wback : boolean = TRUE; let postindex : boolean = FALSE;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| opc | 1 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | imm7 | Rt2 | Rn | Rt | |||||||||||||||||||
| VR | L | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_FP) then EndOfDecode(Decode_UNDEF); end; let wback : boolean = FALSE; let postindex : boolean = FALSE;
| <St1> |
Is the 32-bit name of the first SIMD&FP register to be transferred, encoded in the "Rt" field. |
| <St2> |
Is the 32-bit name of the second SIMD&FP register to be transferred, encoded in the "Rt2" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <Dt1> |
Is the 64-bit name of the first SIMD&FP register to be transferred, encoded in the "Rt" field. |
| <Dt2> |
Is the 64-bit name of the second SIMD&FP register to be transferred, encoded in the "Rt2" field. |
| <Qt1> |
Is the 128-bit name of the first SIMD&FP register to be transferred, encoded in the "Rt" field. |
| <Qt2> |
Is the 128-bit name of the second SIMD&FP register to be transferred, encoded in the "Rt2" field. |
let t : integer{} = UInt(Rt); let t2 : integer{} = UInt(Rt2); let n : integer{} = UInt(Rn); let nontemporal : boolean = FALSE; let scale : integer{} = 2 + (UInt(opc) as integer{0..2}); let datasize : integer{} = 8 << scale; let offset : bits(64) = LSL(SignExtend{64}(imm7), scale); let tagchecked : boolean = wback || n != 31;
AArch64_CheckFPEnabled(); var address : bits(64); let dbytes : integer{} = datasize DIV 8; let privileged : boolean = PSTATE.EL != EL0; let ispair : boolean = TRUE; let accdesc : AccessDescriptor = CreateAccDescASIMD(MemOp_STORE, nontemporal, tagchecked, privileged, ispair); if n == 31 then CheckSPAlignment(); address = SP{64}(); else address = X{64}(n); end; if !postindex then address = AddressAdd(address, offset, accdesc); end; var data : bits(2*datasize); if BigEndian(accdesc.acctype) then data = V{datasize}(t) :: V{datasize}(t2); else data = V{datasize}(t2) :: V{datasize}(t); end; Mem{2*datasize}(address, accdesc) = data; if wback then if postindex then address = AddressAdd(address, offset, accdesc); end; if n == 31 then SP{64}() = address; else X{64}(n) = address; end; end;
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
2026-03_rel 2026-03-26 20:48:11
Copyright © 2010-2026 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.