STR (immediate)

Store register (immediate)

This instruction stores a word or a doubleword from a register to memory. The address that is used for the store is calculated from a base register and an immediate offset. For information about addressing modes, see Load/Store addressing modes.

It has encodings from 3 classes: Post-index , Pre-index and Unsigned offset

Post-index

313029282726252423222120191817161514131211109876543210
1x111000000imm901RnRt
sizeVRopc

Encoding for the 32-bit variant

Applies when (size == 10)

STR <Wt>, [<Xn|SP>], #<simm>

Encoding for the 64-bit variant

Applies when (size == 11)

STR <Xt>, [<Xn|SP>], #<simm>

Decode for all variants of this encoding

let wback : boolean = TRUE; let postindex : boolean = TRUE; let scale : integer{} = UInt(size); let offset : bits(64) = SignExtend{}(imm9);

Pre-index

313029282726252423222120191817161514131211109876543210
1x111000000imm911RnRt
sizeVRopc

Encoding for the 32-bit variant

Applies when (size == 10)

STR <Wt>, [<Xn|SP>, #<simm>]!

Encoding for the 64-bit variant

Applies when (size == 11)

STR <Xt>, [<Xn|SP>, #<simm>]!

Decode for all variants of this encoding

let wback : boolean = TRUE; let postindex : boolean = FALSE; let scale : integer{} = UInt(size); let offset : bits(64) = SignExtend{}(imm9);

Unsigned offset

313029282726252423222120191817161514131211109876543210
1x11100100imm12RnRt
sizeVRopc

Encoding for the 32-bit variant

Applies when (size == 10)

STR <Wt>, [<Xn|SP>{, #<pimm>}]

Encoding for the 64-bit variant

Applies when (size == 11)

STR <Xt>, [<Xn|SP>{, #<pimm>}]

Decode for all variants of this encoding

let wback : boolean = FALSE; let postindex : boolean = FALSE; let scale : integer{} = UInt(size); let offset : bits(64) = LSL(ZeroExtend{64}(imm12), scale);

Assembler Symbols

<Wt>

Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<simm>

Is the signed immediate byte offset, in the range -256 to 255, encoded in the "imm9" field.

<Xt>

Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

<pimm>

For the "32-bit" variant: is the optional positive immediate byte offset, a multiple of 4 in the range 0 to 16380, defaulting to 0 and encoded in the "imm12" field as <pimm>/4.

For the "64-bit" variant: is the optional positive immediate byte offset, a multiple of 8 in the range 0 to 32760, defaulting to 0 and encoded in the "imm12" field as <pimm>/8.

Shared Decode

let t : integer{} = UInt(Rt); let n : integer{} = UInt(Rn); let datasize : integer{} = 8 << scale; let nontemporal : boolean = FALSE; let tagchecked : boolean = wback || n != 31; var c : Constraint; var rt_unknown : boolean = FALSE; if wback && n == t && n != 31 then c = ConstrainUnpredictable(Unpredictable_WBOVERLAPST); assert c IN {Constraint_NONE, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_NONE => rt_unknown = FALSE; // Value stored is original value when Constraint_UNKNOWN => rt_unknown = TRUE; // Value stored is UNKNOWN when Constraint_UNDEF => EndOfDecode(Decode_UNDEF); when Constraint_NOP => EndOfDecode(Decode_NOP); end; end;

Operation

var address : bits(64); let privileged : boolean = PSTATE.EL != EL0; let accdesc : AccessDescriptor = CreateAccDescGPR(MemOp_STORE, nontemporal, privileged, tagchecked, t); if n == 31 then CheckSPAlignment(); address = SP{64}(); else address = X{64}(n); end; if !postindex then address = AddressAdd(address, offset, accdesc); end; var data : bits(datasize); if rt_unknown then data = ARBITRARY : bits(datasize); else data = X{datasize}(t); end; Mem{datasize}(address, accdesc) = data; if wback then if postindex then address = AddressAdd(address, offset, accdesc); end; if n == 31 then SP{64}() = address; else X{64}(n) = address; end; end;

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.


2026-03_rel 2026-03-26 20:48:11

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