Store vector register
This instruction stores a vector register to a memory address generated by a 64-bit scalar base, plus an immediate offset in the range -256 to 255 that is multiplied by the current vector register size in bytes. This instruction is unpredicated.
The store is performed as contiguous byte accesses, with no endian conversion and no guarantee of single-copy atomicity larger than a byte. However, if alignment is checked, then the base register must be aligned to 16 bytes.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | imm9h | 0 | 1 | 0 | imm9l | Rn | Zt | |||||||||||||||
if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; let t : integer = UInt(Zt); let n : integer = UInt(Rn); let imm : integer = SInt(imm9h::imm9l);
| <Zt> |
Is the name of the scalable vector register to be transferred, encoded in the "Zt" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <imm> |
Is the optional signed immediate vector offset, in the range -256 to 255, defaulting to 0, encoded in the "imm9h:imm9l" fields. |
CheckSVEEnabled(); let VL : integer{} = CurrentVL(); let elements : integer = VL DIV 8; var src : bits(VL); var base : bits(64); let offset : integer = imm * elements; let contiguous : boolean = TRUE; let nontemporal : boolean = FALSE; let predicated : boolean = FALSE; let tagchecked : boolean = n != 31; let accdesc : AccessDescriptor = CreateAccDescSVE(MemOp_STORE, nontemporal, contiguous, predicated, tagchecked); if n == 31 then CheckSPAlignment(); base = SP{64}(); else base = X{64}(n); end; src = Z{VL}(t); var addr : bits(64) = AddressAdd(base, offset, accdesc); let aligned : boolean = IsAlignedSize(base, 16); if !aligned && AlignmentEnforced() then let fault : FaultRecord = AlignmentFault(accdesc, addr); AArch64_Abort(fault); end; for e = 0 to elements-1 do AArch64_MemSingle{8}(addr, accdesc, aligned) = src[e*:8]; addr = AddressIncrement(addr, 1, accdesc); end;
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
2026-03_rel 2026-03-26 20:48:11
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