Store ZA array vector
This instruction performs a contiguous store of bytes from a ZA array vector to the memory address generated by a 64-bit scalar base plus an optional immediate offset multiplied by the current vector length in bytes. The ZA array vector is selected by the sum of the vector select register and the same immediate offset, modulo the number of bytes in a Streaming SVE vector.
This instruction is unpredicated.
The store is performed as contiguous byte accesses, with no endian conversion and no guarantee of single-copy atomicity larger than a byte. However, if alignment is checked, then the base register must be aligned to 16 bytes.
This instruction does not require the PE to be in Streaming SVE mode, and it is expected that this instruction will not experience a significant slowdown due to contention with other PEs that are executing in Streaming SVE mode.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | Rv | 0 | 0 | 0 | Rn | 0 | off4 | ||||||||
| op | |||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; let n : integer = UInt(Rn); let v : integer = UInt('011'::Rv); let offset : integer = UInt(off4);
| <Wv> |
Is the 32-bit name of the vector select register W12-W15, encoded in the "Rv" field. |
| <offs> |
Is the vector select offset and optional memory offset, in the range 0 to 15, defaulting to 0, encoded in the "off4" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
CheckSMEAndZAEnabled(); let SVL : integer{} = CurrentSVL(); let dim : integer{} = SVL DIV 8; var base : bits(64); let moffs : integer = offset * dim; var src : bits(SVL); let vbase : bits(32) = X{}(v); let vec : integer = (UInt(vbase) + offset) MOD dim; let contiguous : boolean = TRUE; let nontemporal : boolean = FALSE; let tagchecked : boolean = n != 31; let accdesc : AccessDescriptor = CreateAccDescSME(MemOp_STORE, nontemporal, contiguous, tagchecked); if n == 31 then CheckSPAlignment(); base = SP{64}(); else base = X{64}(n); end; src = ZAvector{SVL}(vec); var addr : bits(64) = AddressAdd(base, moffs, accdesc); let aligned : boolean = IsAlignedSize(base, 16); if !aligned && AlignmentEnforced() then let fault : FaultRecord = AlignmentFault(accdesc, addr); AArch64_Abort(fault); end; for e = 0 to dim-1 do AArch64_MemSingle{8}(addr, accdesc, aligned) = src[e*:8]; addr = AddressIncrement(addr, 1, accdesc); end;
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
2026-03_rel 2026-03-26 20:48:11
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