Store unprivileged pair of registers
This instruction calculates an address from a base register value and an immediate offset, and stores two 64-bit doublewords to the calculated address, from two registers.
Explicit Memory effects produced by the instruction behave as if the instruction was executed at EL0 if the Effective value of PSTATE.UAO is 0 and either:
Otherwise, the Explicit Memory effects operate with the restrictions determined by the Exception level at which the instruction is executed.
For information about addressing modes, see Load/Store addressing modes.
It has encodings from 3 classes: Post-index , Pre-index and Signed offset
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | imm7 | Rt2 | Rn | Rt | ||||||||||||||||||
| opc | VR | L | |||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_LSUI) then EndOfDecode(Decode_UNDEF); end; let wback : boolean = TRUE; let postindex : boolean = TRUE;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | imm7 | Rt2 | Rn | Rt | ||||||||||||||||||
| opc | VR | L | |||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_LSUI) then EndOfDecode(Decode_UNDEF); end; let wback : boolean = TRUE; let postindex : boolean = FALSE;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | imm7 | Rt2 | Rn | Rt | ||||||||||||||||||
| opc | VR | L | |||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_LSUI) then EndOfDecode(Decode_UNDEF); end; let wback : boolean = FALSE; let postindex : boolean = FALSE;
STTP has the same CONSTRAINED UNPREDICTABLE behavior as STP. See Architectural Constraints on UNPREDICTABLE behaviors, and particularly STP.
| <Xt1> |
Is the 64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field. |
| <Xt2> |
Is the 64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
let t : integer{} = UInt(Rt); let t2 : integer{} = UInt(Rt2); let n : integer{} = UInt(Rn); let nontemporal : boolean = FALSE; let scale : integer{} = 2 + UInt(opc[1]); let datasize : integer{} = 64; let offset : bits(64) = LSL(SignExtend{64}(imm7), scale); let tagchecked : boolean = wback || n != 31; var rt_unknown : boolean = FALSE; if wback && (t == n || t2 == n) && n != 31 then let c : Constraint = ConstrainUnpredictable(Unpredictable_WBOVERLAPST); assert c IN {Constraint_NONE, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_NONE => rt_unknown = FALSE; // Value stored is pre-writeback when Constraint_UNKNOWN => rt_unknown = TRUE; // Value stored is UNKNOWN when Constraint_UNDEF => EndOfDecode(Decode_UNDEF); when Constraint_NOP => EndOfDecode(Decode_NOP); end; end;
var address : bits(64); var data1 : bits(datasize); var data2 : bits(datasize); let dbytes : integer{} = datasize DIV 8; let privileged : boolean = AArch64_IsUnprivAccessPriv(); let ispair : boolean = TRUE; let accdesc : AccessDescriptor = CreateAccDescGPR(MemOp_STORE, nontemporal, privileged, tagchecked, ispair, t, t2); if n == 31 then CheckSPAlignment(); address = SP{64}(); else address = X{64}(n); end; if !postindex then address = AddressAdd(address, offset, accdesc); end; if rt_unknown && t == n then data1 = ARBITRARY : bits(datasize); else data1 = X{datasize}(t); end; if rt_unknown && t2 == n then data2 = ARBITRARY : bits(datasize); else data2 = X{datasize}(t2); end; let data : bits(2*datasize) = (if BigEndian(accdesc.acctype) then data1::data2 else data2::data1); Mem{2 * datasize}(address, accdesc) = data; if wback then if postindex then address = AddressAdd(address, offset, accdesc); end; if n == 31 then SP{64}() = address; else X{64}(n) = address; end; end;
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
2026-03_rel 2026-03-26 20:48:11
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