SUMLALL (multiple and single vector)

Multi-vector signed by unsigned 8-bit integer multiply-add by vector to 32-bit integer

This instruction multiplies each signed 8-bit element in the two or four first source vectors by each unsigned 8-bit element in the second source vector, widens each product to 32 bits, and destructively adds these values to the corresponding 32-bit elements of the ZA quad-vector groups.

The quad-vector group within each half of or each quarter of the ZA array is selected by the sum of the vector select register and offset range, modulo half or quarter the number of ZA array vectors.

The vector group symbol, VGx2 or VGx4, indicates that the ZA operand consists of two or four ZA quad-vector groups respectively. The vector group symbol is preferred for disassembly, but optional in assembler source code.

This instruction is unpredicated.

It has encodings from 2 classes: Two ZA quad-vectors and Four ZA quad-vectors

Two ZA quad-vectors
(FEAT_SME2)

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME2) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 32; let v : integer = UInt('010'::Rv); let n : integer = UInt(Zn); let m : integer = UInt('0'::Zm); let offset : integer = UInt(o1::'00'); let nreg : integer{} = 2;

Four ZA quad-vectors
(FEAT_SME2)

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME2) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 32; let v : integer = UInt('010'::Rv); let n : integer = UInt(Zn); let m : integer = UInt('0'::Zm); let offset : integer = UInt(o1::'00'); let nreg : integer{} = 4;