Trace synchronization barrier
This instruction is a barrier that synchronizes the trace operations of instructions, see Trace Synchronization Barrier (TSB).
If FEAT_TRF is not implemented, this instruction executes as a NOP.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 |
| CRm | op2 | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_TRF) then EndOfDecode(Decode_NOP); end;
if IsFeatureImplemented(FEAT_FGT2) && IsFeatureImplemented(FEAT_TRBEv1p1) then let trap_to_el2 : boolean = (PSTATE.EL IN {EL0, EL1} && EL2Enabled() && !IsInHost() && (!HaveEL(EL3) || SCR_EL3().FGTEn2 == '1') && HFGITR2_EL2().TSBCSYNC == '1'); if trap_to_el2 then let target_el : bits(2) = EL2; let iss : bits(25) = 0x4[24:0]; AArch64_OtherInstrTrap(target_el, iss); end; end; TraceSynchronizationBarrier();
2026-03_rel 2026-03-26 20:48:11
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