UCVTF (scalar, fixed-point)

Unsigned fixed-point convert to floating-point (scalar)

This instruction converts the unsigned value in the 32-bit or 64-bit general-purpose source register to a floating-point value using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.

This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exceptions and exception traps.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

313029282726252423222120191817161514131211109876543210
sf0011110ftype000011scaleRnRd
Srmodeopcode

Encoding for the 32-bit to half-precision variant
(FEAT_FP16)

Applies when (sf == 0 && ftype == 11)

UCVTF <Hd>, <Wn>, #<fbits>

Encoding for the 64-bit to half-precision variant
(FEAT_FP16)

Applies when (sf == 1 && ftype == 11)

UCVTF <Hd>, <Xn>, #<fbits>

Encoding for the 32-bit to single-precision variant
(FEAT_FP)

Applies when (sf == 0 && ftype == 00)

UCVTF <Sd>, <Wn>, #<fbits>

Encoding for the 64-bit to single-precision variant
(FEAT_FP)

Applies when (sf == 1 && ftype == 00)

UCVTF <Sd>, <Xn>, #<fbits>

Encoding for the 32-bit to double-precision variant
(FEAT_FP)

Applies when (sf == 0 && ftype == 01)

UCVTF <Dd>, <Wn>, #<fbits>

Encoding for the 64-bit to double-precision variant
(FEAT_FP)

Applies when (sf == 1 && ftype == 01)

UCVTF <Dd>, <Xn>, #<fbits>

Decode for all variants of this encoding

if !IsFeatureImplemented(FEAT_FP) then EndOfDecode(Decode_UNDEF); end; if ftype == '10' then EndOfDecode(Decode_UNDEF); end; if ftype == '11' && !IsFeatureImplemented(FEAT_FP16) then EndOfDecode(Decode_UNDEF); end; if sf == '0' && scale[5] == '0' then EndOfDecode(Decode_UNDEF); end; let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let intsize : integer{} = 32 << UInt(sf); let decode_fltsize : integer{} = 8 << UInt(ftype XOR '10'); let fracbits : integer = 64 - UInt(scale); let unsigned : boolean = TRUE;

Assembler Symbols

<Hd>

Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.

<Wn>

Is the 32-bit name of the general-purpose source register, encoded in the "Rn" field.

<fbits>

For the "32-bit to double-precision", "32-bit to half-precision", and "32-bit to single-precision" variants: is the number of bits after the binary point in the fixed-point source, in the range 1 to 32, encoded as 64 minus "scale".

For the "64-bit to double-precision", "64-bit to half-precision", and "64-bit to single-precision" variants: is the number of bits after the binary point in the fixed-point source, in the range 1 to 64, encoded as 64 minus "scale".

<Xn>

Is the 64-bit name of the general-purpose source register, encoded in the "Rn" field.

<Sd>

Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.

<Dd>

Is the 64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.

Operation

AArch64_CheckFPEnabled(); let merge : boolean = IsMerging(FPCR()); let fltsize : integer{} = if merge then 128 else decode_fltsize; var fltval : bits(fltsize) = if merge then V{fltsize}(d) else Zeros{fltsize}; let intval : bits(intsize) = X{}(n); let rounding : FPRounding = FPRoundingMode(FPCR()); fltval[0+:decode_fltsize] = FixedToFP{decode_fltsize, intsize}(intval, fracbits, unsigned, FPCR(), rounding); V{fltsize}(d) = fltval;


2026-03_rel 2026-03-26 20:48:11

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