UCVTF (scalar SIMD&FP)

Unsigned integer convert to floating-point (scalar SIMD&FP)

This instruction converts the unsigned integer value in the SIMD&FP source register to a floating-point value using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.

This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exceptions and exception traps.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Integer
(FEAT_FPRCVT)

313029282726252423222120191817161514131211109876543210
sf0011110ftype111101000000RnRd
Srmodeopcode

Encoding for the 32-bit to half-precision variant

Applies when (sf == 0 && ftype == 11)

UCVTF <Hd>, <Sn>

Encoding for the 32-bit to double-precision variant

Applies when (sf == 0 && ftype == 01)

UCVTF <Dd>, <Sn>

Encoding for the 64-bit to half-precision variant

Applies when (sf == 1 && ftype == 11)

UCVTF <Hd>, <Dn>

Encoding for the 64-bit to single-precision variant

Applies when (sf == 1 && ftype == 00)

UCVTF <Sd>, <Dn>

Decode for all variants of this encoding

if !IsFeatureImplemented(FEAT_FPRCVT) then EndOfDecode(Decode_UNDEF); end; let d : integer = UInt(Rd); let n : integer = UInt(Rn); let intsize : integer{} = 32 << UInt(sf); let fltsize : integer{} = 8 << UInt(ftype XOR '10'); let rounding : FPRounding = FPRoundingMode(FPCR());

Assembler Symbols

<Hd>

Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.

<Sn>

Is the 32-bit name of the SIMD&FP source register, encoded in the "Rn" field.

<Dd>

Is the 64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.

<Dn>

Is the 64-bit name of the SIMD&FP source register, encoded in the "Rn" field.

<Sd>

Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.

Operation

AArch64_CheckFPEnabled(); var fltval : bits(fltsize); var intval : bits(intsize); let merge : boolean = IsMerging(FPCR()); var result : bits(128) = if merge then V{128}(d) else Zeros{128}; intval = V{intsize}(n); fltval = FixedToFP{fltsize, intsize}(intval, 0, TRUE, FPCR(), rounding); result[0+:fltsize] = fltval; V{128}(d) = result;


2026-03_rel 2026-03-26 20:48:11

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