Multi-vector unsigned 16-bit integer dot product by vector to 32-bit integer
This instruction calculates the dot product of two unsigned 16-bit integer values held in each 32-bit element of the two or four first source vectors and two unsigned 16-bit integer values in the corresponding 32-bit element of the second source vector. The widened dot product result is destructively added to the corresponding 32-bit element of the ZA single-vector groups.
The single-vector group within each half of or each quarter of the ZA array is selected by the sum of the vector select register and offset, modulo half or quarter the number of ZA array vectors.
The vector group symbol, VGx2 or VGx4, indicates that the ZA operand consists of two or four ZA single-vector groups respectively. The vector group symbol is preferred for disassembly, but optional in assembler source code.
This instruction is unpredicated.
It has encodings from 2 classes: Two ZA single-vectors and Four ZA single-vectors
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | Zm | 0 | Rv | 1 | 0 | 1 | Zn | 1 | 1 | off3 | ||||||||||
| U | |||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SME2) then EndOfDecode(Decode_UNDEF); end; let v : integer = UInt('010'::Rv); let esize : integer{} = 32; let n : integer = UInt(Zn); let m : integer = UInt('0'::Zm); let offset : integer = UInt(off3); let nreg : integer{} = 2;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | Zm | 0 | Rv | 1 | 0 | 1 | Zn | 1 | 1 | off3 | ||||||||||
| U | |||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SME2) then EndOfDecode(Decode_UNDEF); end; let v : integer = UInt('010'::Rv); let esize : integer{} = 32; let n : integer = UInt(Zn); let m : integer = UInt('0'::Zm); let offset : integer = UInt(off3); let nreg : integer{} = 4;
| <Wv> |
Is the 32-bit name of the vector select register W8-W11, encoded in the "Rv" field. |
| <offs> |
Is the vector select offset, in the range 0 to 7, encoded in the "off3" field. |
| <Zn1> |
Is the name of the first scalable vector register of the first source multi-vector group, encoded as "Zn". |
| <Zn2> |
Is the name of the second scalable vector register of the first source multi-vector group, encoded as "Zn" plus 1 modulo 32. |
| <Zm> |
Is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field. |
| <Zn4> |
Is the name of the fourth scalable vector register of the first source multi-vector group, encoded as "Zn" plus 3 modulo 32. |
CheckStreamingSVEAndZAEnabled(); let VL : integer{} = CurrentVL(); let elements : integer = VL DIV esize; let vectors : integer = VL DIV 8; let vstride : integer = vectors DIV nreg; let vbase : bits(32) = X{}(v); var vec : integer = (UInt(vbase) + offset) MOD vstride; var result : bits(VL); for r = 0 to nreg-1 do let operand1 : bits(VL) = Z{}((n+r) MOD 32); let operand2 : bits(VL) = Z{}(m); let operand3 : bits(VL) = ZAvector{}(vec); for e = 0 to elements-1 do var sum : bits(esize) = operand3[e*:esize]; for i = 0 to 1 do let element1 : integer = UInt(operand1[(2 * e + i)*:(esize DIV 2)]); let element2 : integer = UInt(operand2[(2 * e + i)*:(esize DIV 2)]); sum = sum + element1 * element2; end; result[e*:esize] = sum; end; ZAvector{VL}(vec) = result; vec = vec + vstride; end;
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
2026-03_rel 2026-03-26 20:48:11
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