UMLALL (multiple and indexed vector) -- A64

This instruction multiplies each unsigned 8-bit or 16-bit element in the one, two, or four first source vectors by each unsigned 8-bit or 16-bit indexed element of the second source vector, widens each product to 32 bits or 64 bits, and destructively adds these values to the corresponding 32-bit or 64-bit elements of the ZA quad-vector groups.

The elements within the second source vector are specified using an immediate element index that selects the same element position within each 128-bit vector segment. The index range is from 0 to one less than the number of elements per 128-bit segment.

The quad-vector group within all of, each half of, or each quarter of the ZA array is selected by the sum of the vector select register and offset range, modulo all, half, or quarter the number of ZA array vectors.

The vector group symbol, VGx2 or VGx4, indicates that the ZA operand consists of two or four ZA quad-vector groups respectively. The vector group symbol is preferred for disassembly, but optional in assembler source code.

ID_AA64SMFR0_EL1.I16I64 indicates whether the 16-bit integer variant is implemented.

One ZA quad-vector of 32-bit elements
(FEAT_SME2)

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME2) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 32; let v : integer = UInt('010'::Rv); let n : integer = UInt(Zn); let m : integer = UInt('0'::Zm); let offset : integer = UInt(off2::'00'); let index : integer = UInt(i4h::i4l); let nreg : integer{} = 1;

One ZA quad-vector of 64-bit elements
(FEAT_SME2 && FEAT_SME_I16I64)

Decode for this encoding

if !(IsFeatureImplemented(FEAT_SME2) && IsFeatureImplemented(FEAT_SME_I16I64)) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 64; let v : integer = UInt('010'::Rv); let n : integer = UInt(Zn); let m : integer = UInt('0'::Zm); let offset : integer = UInt(off2::'00'); let index : integer = UInt(i3h::i3l); let nreg : integer{} = 1;

Two ZA quad-vectors of 32-bit elements
(FEAT_SME2)

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME2) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 32; let v : integer = UInt('010'::Rv); let n : integer = UInt(Zn::'0'); let m : integer = UInt('0'::Zm); let offset : integer = UInt(o1::'00'); let index : integer = UInt(i4h::i4l); let nreg : integer{} = 2;

Two ZA quad-vectors of 64-bit elements
(FEAT_SME2 && FEAT_SME_I16I64)

Decode for this encoding

if !(IsFeatureImplemented(FEAT_SME2) && IsFeatureImplemented(FEAT_SME_I16I64)) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 64; let v : integer = UInt('010'::Rv); let n : integer = UInt(Zn::'0'); let m : integer = UInt('0'::Zm); let offset : integer = UInt(o1::'00'); let index : integer = UInt(i3h::i3l); let nreg : integer{} = 2;

Four ZA quad-vectors of 32-bit elements
(FEAT_SME2)

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME2) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 32; let v : integer = UInt('010'::Rv); let n : integer = UInt(Zn::'00'); let m : integer = UInt('0'::Zm); let offset : integer = UInt(o1::'00'); let index : integer = UInt(i4h::i4l); let nreg : integer{} = 4;

Four ZA quad-vectors of 64-bit elements
(FEAT_SME2 && FEAT_SME_I16I64)

Decode for this encoding

if !(IsFeatureImplemented(FEAT_SME2) && IsFeatureImplemented(FEAT_SME_I16I64)) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 64; let v : integer = UInt('010'::Rv); let n : integer = UInt(Zn::'00'); let m : integer = UInt('0'::Zm); let offset : integer = UInt(o1::'00'); let index : integer = UInt(i3h::i3l); let nreg : integer{} = 4;

Assembler Symbols

<Wv>	Is the 32-bit name of the vector select register W8-W11, encoded in the "Rv" field.

<offs1>	For the "One ZA quad-vector of 32-bit elements" and "One ZA quad-vector of 64-bit elements" variants: is the first vector select offset, encoded as "off2" field times 4.
	For the "Four ZA quad-vectors of 32-bit elements", "Four ZA quad-vectors of 64-bit elements", "Two ZA quad-vectors of 32-bit elements", and "Two ZA quad-vectors of 64-bit elements" variants: is the first vector select offset, encoded as "o1" field times 4.

<offs4>	For the "One ZA quad-vector of 32-bit elements" and "One ZA quad-vector of 64-bit elements" variants: is the fourth vector select offset, encoded as "off2" field times 4 plus 3.
	For the "Four ZA quad-vectors of 32-bit elements", "Four ZA quad-vectors of 64-bit elements", "Two ZA quad-vectors of 32-bit elements", and "Two ZA quad-vectors of 64-bit elements" variants: is the fourth vector select offset, encoded as "o1" field times 4 plus 3.

<Zn>	Is the name of the first source scalable vector register, encoded in the "Zn" field.

<Zm>	Is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.

<index>	For the "Four ZA quad-vectors of 32-bit elements", "One ZA quad-vector of 32-bit elements", and "Two ZA quad-vectors of 32-bit elements" variants: is the element index, in the range 0 to 15, encoded in the "i4h:i4l" fields.
	For the "Four ZA quad-vectors of 64-bit elements", "One ZA quad-vector of 64-bit elements", and "Two ZA quad-vectors of 64-bit elements" variants: is the element index, in the range 0 to 7, encoded in the "i3h:i3l" fields.

<Zn1>	For the "Two ZA quad-vectors of 32-bit elements" and "Two ZA quad-vectors of 64-bit elements" variants: is the name of the first scalable vector register of the first source multi-vector group, encoded as "Zn" times 2.
	For the "Four ZA quad-vectors of 32-bit elements" and "Four ZA quad-vectors of 64-bit elements" variants: is the name of the first scalable vector register of the first source multi-vector group, encoded as "Zn" times 4.

<Zn2>

Is the name of the second scalable vector register of the first source multi-vector group, encoded as "Zn" times 2 plus 1.

<Zn4>

Is the name of the fourth scalable vector register of the first source multi-vector group, encoded as "Zn" times 4 plus 3.

Operation

CheckStreamingSVEAndZAEnabled(); let VL : integer{} = CurrentVL(); let elements : integer = VL DIV esize; let vectors : integer = VL DIV 8; let vstride : integer = vectors DIV nreg; let eltspersegment : integer = 128 DIV esize; let vbase : bits(32) = X{}(v); var vec : integer = (UInt(vbase) + offset) MOD vstride; var result : bits(VL); vec = vec - (vec MOD 4); for r = 0 to nreg-1 do let operand1 : bits(VL) = Z{}(n+r); let operand2 : bits(VL) = Z{}(m); for i = 0 to 3 do let operand3 : bits(VL) = ZAvector{}(vec + i); for e = 0 to elements-1 do let segmentbase : integer = e - (e MOD eltspersegment); let s : integer = 4 * segmentbase + index; let element1 : integer = UInt(operand1[(4 * e + i)*:(esize DIV 4)]); let element2 : integer = UInt(operand2[s*:(esize DIV 4)]); let product : bits(esize) = (element1 * element2)[esize-1:0]; result[e*:esize] = operand3[e*:esize] + product; end; ZAvector{VL}(vec + i) = result; end; vec = vec + vstride; end;

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.

2026-03_rel 2026-03-26 20:48:11