UQADD

Unsigned saturating add

This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

It has encodings from 2 classes: Scalar and Vector

Scalar
(FEAT_AdvSIMD)

313029282726252423222120191817161514131211109876543210
01111110size1Rm000011RnRd
Uopcode

Encoding

UQADD <V><d>, <V><n>, <V><m>

Decode for this encoding

if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end; let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let m : integer{} = UInt(Rm); let esize : integer{} = 8 << UInt(size); let datasize : integer{} = esize; let elements : integer = 1; let unsigned : boolean = TRUE;

Vector
(FEAT_AdvSIMD)

313029282726252423222120191817161514131211109876543210
0Q101110size1Rm000011RnRd
Uopcode

Encoding

UQADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

Decode for this encoding

if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end; if size::Q == '110' then EndOfDecode(Decode_UNDEF); end; let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let m : integer{} = UInt(Rm); let esize : integer{} = 8 << UInt(size); let datasize : integer{} = 64 << UInt(Q); let elements : integer = datasize DIV esize; let unsigned : boolean = TRUE;

Assembler Symbols

<V>

Is a width specifier, encoded in size:

size <V>
00 B
01 H
10 S
11 D
<d>

Is the number of the SIMD&FP destination register, encoded in the "Rd" field.

<n>

Is the number of the first SIMD&FP source register, encoded in the "Rn" field.

<m>

Is the number of the second SIMD&FP source register, encoded in the "Rm" field.

<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T>

Is an arrangement specifier, encoded in (size :: Q):

size Q <T>
00 0 8B
00 1 16B
01 0 4H
01 1 8H
10 0 2S
10 1 4S
11 0 RESERVED
11 1 2D
<Vn>

Is the name of the first SIMD&FP source register, encoded in the "Rn" field.

<Vm>

Is the name of the second SIMD&FP source register, encoded in the "Rm" field.

Operation

AArch64_CheckFPAdvSIMDEnabled(); let operand1 : bits(datasize) = V{}(n); let operand2 : bits(datasize) = V{}(m); var result : bits(datasize); var element1 : integer; var element2 : integer; var sum : integer; var sat : boolean; for e = 0 to elements-1 do element1 = UInt(operand1[e*:esize]); element2 = UInt(operand2[e*:esize]); sum = element1 + element2; (result[e*:esize], sat) = SatQ{esize}(sum, unsigned); if sat then FPSR().QC = '1'; end; end; V{datasize}(d) = result;


2026-03_rel 2026-03-26 20:48:11

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