UQADD (vectors, unpredicated) -- A64

This instruction performs an unsigned saturating addition of all elements of the first source vector to the corresponding elements of the second source vector, and places the results in the corresponding elements of the destination vector. Each result element is saturated to the N-bit element's unsigned integer range 0 to (2^N)-1. This instruction is unpredicated.

SVE
(FEAT_SVE || FEAT_SME)

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8 << UInt(size); let n : integer = UInt(Zn); let m : integer = UInt(Zm); let d : integer = UInt(Zd); let unsigned : boolean = TRUE;

Assembler Symbols

<Zd>	Is the name of the destination scalable vector register, encoded in the "Zd" field.

<T>

Is the size specifier, encoded in size:

size	<T>
00	B
01	H
10	S
11	D

<Zn>	Is the name of the first source scalable vector register, encoded in the "Zn" field.

<Zm>	Is the name of the second source scalable vector register, encoded in the "Zm" field.

Operation

CheckSVEEnabled(); let VL : integer{} = CurrentVL(); let elements : integer = VL DIV esize; let operand1 : bits(VL) = Z{}(n); let operand2 : bits(VL) = Z{}(m); var result : bits(VL); for e = 0 to elements-1 do let op1elt : bits(esize) = operand1[e*:esize]; let op2elt : bits(esize) = operand2[e*:esize]; if unsigned then let element1 : integer = UInt(op1elt); let element2 : integer = UInt(op2elt); (result[e*:esize], -) = UnsignedSatQ{esize}(element1 + element2); else let element1 : integer = SInt(op1elt); let element2 : integer = SInt(op2elt); (result[e*:esize], -) = SignedSatQ{esize}(element1 + element2); end; end; Z{VL}(d) = result;

2026-03_rel 2026-03-26 20:48:11

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	0	0	0	1	0	0	size		1	Zm					0	0	0	1	0	1	Zn					Zd
																					U