UQINCD (vector)

Unsigned saturating increment vector by multiple of 64-bit predicate constraint element count

This instruction determines the number of active 64-bit elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to increment all destination vector elements. The results are saturated to the 64-bit unsigned integer range.

The named predicate constraint limits the number of active elements in a single predicate to:

Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.

SVE
(FEAT_SVE || FEAT_SME)

313029282726252423222120191817161514131211109876543210
000001001110imm4110001patternZdn
sizeDU

Encoding

UQINCD <Zdn>.D{, <pattern>{, MUL #<imm>}}

Decode for this encoding

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 64; let dn : integer = UInt(Zdn); let pat : bits(5) = pattern; let imm : integer = UInt(imm4) + 1; let unsigned : boolean = TRUE;

Assembler Symbols

<Zdn>

Is the name of the source and destination scalable vector register, encoded in the "Zdn" field.

<pattern>

Is the optional pattern specifier, defaulting to ALL, encoded in pattern:

pattern <pattern>
00000 POW2
00001 VL1
00010 VL2
00011 VL3
00100 VL4
00101 VL5
00110 VL6
00111 VL7
01000 VL8
01001 VL16
01010 VL32
01011 VL64
01100 VL128
01101 VL256
0111x #uimm5
1xx00 #uimm5
1x0x1 #uimm5
1x010 #uimm5
101x1 #uimm5
10110 #uimm5
11101 MUL4
11110 MUL3
11111 ALL
<imm>

Is the immediate multiplier, in the range 1 to 16, defaulting to 1, encoded in the "imm4" field.

Operation

CheckSVEEnabled(); let VL : integer{} = CurrentVL(); let elements : integer = VL DIV esize; let count : integer = DecodePredCount(pat, esize); let operand1 : bits(VL) = Z{}(dn); var result : bits(VL); for e = 0 to elements-1 do let op1elt : bits(esize) = operand1[e*:esize]; if unsigned then (result[e*:esize], -) = UnsignedSatQ{esize}(UInt(op1elt) + (count * imm)); else (result[e*:esize], -) = SignedSatQ{esize}(SInt(op1elt) + (count * imm)); end; end; Z{VL}(dn) = result;

Operational information

This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is CONSTRAINED UNPREDICTABLE:


2026-03_rel 2026-03-26 20:48:11

Copyright © 2010-2026 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.