Unsigned rounding shift right by immediate
This instruction shifts right by immediate each active unsigned element of the source vector, and destructively places the rounded results in the corresponding elements of the source vector. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. Inactive elements in the destination vector register remain unmodified.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | tszh | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | Pg | tszl | imm3 | Zdn | ||||||||||
| opc | L | U | |||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; let tsize : bits(4) = tszh::tszl; if tsize == '0000' then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8 << HighestSetBitNZ(tsize); let g : integer = UInt(Pg); let dn : integer = UInt(Zdn); let shift : integer = (2 * esize) - UInt(tsize::imm3);
| <Zdn> |
Is the name of the source and destination scalable vector register, encoded in the "Zdn" field. |
| <T> |
Is the size specifier,
encoded in
|
| <Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
| <const> |
Is the immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3". |
CheckSVEEnabled(); let VL : integer{} = CurrentVL(); let PL : integer{} = VL DIV 8; let elements : integer = VL DIV esize; let operand1 : bits(VL) = Z{}(dn); let mask : bits(PL) = P{}(g); var result : bits(VL); for e = 0 to elements-1 do let element1 : integer = UInt(operand1[e*:esize]); if ActivePredicateElement{PL}(mask, e, esize) then let res : integer = (element1 + (1 << (shift - 1))) >> shift; result[e*:esize] = res[esize-1:0]; else result[e*:esize] = operand1[e*:esize]; end; end; Z{VL}(dn) = result;
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is CONSTRAINED UNPREDICTABLE:
2026-03_rel 2026-03-26 20:48:11
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