Unsigned by signed 8-bit integer dot product to 32-bit integer
This instruction calculates the dot product of a group of four unsigned 8-bit integer values held in each 32-bit element of the first source vector multiplied by a group of four signed 8-bit integer values in the corresponding 32-bit element of the second source vector, and then destructively adds the widened dot product to the corresponding 32-bit element of the destination vector.
This instruction is unpredicated.
ID_AA64ZFR0_EL1.I8MM indicates whether this instruction is implemented.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | Zm | 0 | 1 | 1 | 1 | 1 | 0 | Zn | Zda | ||||||||||||
| size | |||||||||||||||||||||||||||||||
if ((!IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME)) || !IsFeatureImplemented(FEAT_I8MM)) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 32; let n : integer = UInt(Zn); let m : integer = UInt(Zm); let da : integer = UInt(Zda);
| <Zda> |
Is the name of the third source and destination scalable vector register, encoded in the "Zda" field. |
| <Zn> |
Is the name of the first source scalable vector register, encoded in the "Zn" field. |
| <Zm> |
Is the name of the second source scalable vector register, encoded in the "Zm" field. |
CheckSVEEnabled(); let VL : integer{} = CurrentVL(); let elements : integer = VL DIV esize; let operand1 : bits(VL) = Z{}(n); let operand2 : bits(VL) = Z{}(m); let operand3 : bits(VL) = Z{}(da); var result : bits(VL); for e = 0 to elements-1 do var res : bits(esize) = operand3[e*:esize]; for i = 0 to 3 do let element1 : integer = UInt(operand1[(4 * e + i)*:(esize DIV 4)]); let element2 : integer = SInt(operand2[(4 * e + i)*:(esize DIV 4)]); res = res + element1 * element2; end; result[e*:esize] = res; end; Z{VL}(da) = result;
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is CONSTRAINED UNPREDICTABLE:
2026-03_rel 2026-03-26 20:48:11
Copyright © 2010-2026 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.