Unsigned shift right (immediate)
This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSHR.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
It has encodings from 2 classes: Scalar and Vector
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | x | x | x | immb | 0 | 0 | 0 | 0 | 0 | 1 | Rn | Rd | ||||||||||
| U | immh | o1 | o0 | ||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end; if immh[3] != '1' then EndOfDecode(Decode_UNDEF); end; let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let esize : integer{} = 8 << 3; let datasize : integer{} = esize; let elements : integer = 1; let shift : integer = (esize * 2) - UInt(immh::immb); let unsigned : boolean = TRUE; let round : boolean = FALSE;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | Q | 1 | 0 | 1 | 1 | 1 | 1 | 0 | != 0000 | immb | 0 | 0 | 0 | 0 | 0 | 1 | Rn | Rd | |||||||||||||
| U | immh | o1 | o0 | ||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end; if immh[3]::Q == '10' then EndOfDecode(Decode_UNDEF); end; let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let esize : integer{} = 8 << HighestSetBitNZ(immh); let datasize : integer{} = 64 << UInt(Q); let elements : integer = datasize DIV esize; let shift : integer = (esize * 2) - UInt(immh::immb); let unsigned : boolean = TRUE; let round : boolean = FALSE;
| <d> |
Is the number of the SIMD&FP destination register, encoded in the "Rd" field. |
| <n> |
Is the number of the SIMD&FP source register, encoded in the "Rn" field. |
| <Vd> |
Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
| <T> |
Is an arrangement specifier,
encoded in
|
| <Vn> |
Is the name of the SIMD&FP source register, encoded in the "Rn" field. |
AArch64_CheckFPAdvSIMDEnabled(); let operand : bits(datasize) = V{}(n); var result : bits(datasize); var element : integer; for e = 0 to elements-1 do let opelt : bits(esize) = operand[e*:esize]; if unsigned then element = RShr(UInt(opelt), shift, round); else element = RShr(SInt(opelt), shift, round); end; result[e*:esize] = element[esize-1:0]; end; V{datasize}(d) = result;
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
2026-03_rel 2026-03-26 20:48:11
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