Unsigned by signed integer quarter-tile sum of outer products, subtracting
This instruction generates four independent quarter-tile unsigned by signed integer sums of outer products from the sub-matrices in the half-vectors of the one or two first and second source vectors and subtracts the results from the corresponding elements of a 32-bit or 64-bit element ZA tile.
In case of the 8-bit integer variant, each of the quarter-tile sums of outer products is generated by multiplying the SVLS÷2 × 4 sub-matrix of 8-bit unsigned values held in the half-vectors of the first source vectors by the 4 × SVLS÷2 sub-matrix of 8-bit signed values held in the half-vectors of the second source vectors. Each 32-bit container of the half-vectors in the first source vectors holds 4 elements of each row of a SVLS÷2 × 4 sub-matrix. Similarly, each 32-bit container of the half-vectors in the second source vector holds 4 elements of each column of a 4 × SVLS÷2 sub-matrix.
In case of the 16-bit integer variant, each of the quarter-tile sums of outer products is generated by multiplying the SVLD÷2 × 4 sub-matrix of 16-bit unsigned values held in the half-vectors of the first source vectors by the 4 × SVLD÷2 sub-matrix of 16-bit signed values held in the half-vectors of the second source vectors. Each 64-bit container of the half-vectors in the first source vectors holds 4 elements of each row of a SVLD÷2 × 4 sub-matrix. Similarly, each 64-bit container of the half-vectors in the second source vector holds 4 elements of each column of a 4 × SVLD÷2 sub-matrix.
The resulting quarter-tile SVLS÷2 × SVLS÷2 widened 32-bit integer sums of outer products in case of the 8-bit integer variant or SVLD÷2 × SVLD÷2 widened 64-bit integer sums of outer products in case of the 16-bit integer variant are then destructively subtracted from the 32-bit or 64-bit integer destination tile respectively.
This is equivalent to performing a 4-way dot product and subtract from each of the destination tile elements.
This instruction is unpredicated.
It has encodings from 8 classes: 32-bit, single and multiple vectors , 32-bit, single vectors , 32-bit, multiple and single vectors , 32-bit, multiple vectors , 64-bit, single and multiple vectors , 64-bit, single vectors , 64-bit, multiple and single vectors and 64-bit, multiple vectors
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | Zm | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | Zn | 0 | 1 | 0 | 0 | ZAda | |||||
| u0 | u1 | M | N | S | |||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SME_MOP4) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 32; let n : integer = UInt('0'::Zn::'0'); let m : integer = UInt('1'::Zm::'0'); let nreg : integer{} = 1; let mreg : integer = 2; let da : integer = UInt(ZAda); let sub_op : boolean = TRUE; let op1_unsigned : boolean = TRUE; let op2_unsigned : boolean = FALSE;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | Zm | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | Zn | 0 | 1 | 0 | 0 | ZAda | |||||
| u0 | u1 | M | N | S | |||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SME_MOP4) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 32; let n : integer = UInt('0'::Zn::'0'); let m : integer = UInt('1'::Zm::'0'); let nreg : integer{} = 1; let mreg : integer = 1; let da : integer = UInt(ZAda); let sub_op : boolean = TRUE; let op1_unsigned : boolean = TRUE; let op2_unsigned : boolean = FALSE;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | Zm | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | Zn | 0 | 1 | 0 | 0 | ZAda | |||||
| u0 | u1 | M | N | S | |||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SME_MOP4) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 32; let n : integer = UInt('0'::Zn::'0'); let m : integer = UInt('1'::Zm::'0'); let nreg : integer{} = 2; let mreg : integer = 1; let da : integer = UInt(ZAda); let sub_op : boolean = TRUE; let op1_unsigned : boolean = TRUE; let op2_unsigned : boolean = FALSE;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | Zm | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | Zn | 0 | 1 | 0 | 0 | ZAda | |||||
| u0 | u1 | M | N | S | |||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SME_MOP4) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 32; let n : integer = UInt('0'::Zn::'0'); let m : integer = UInt('1'::Zm::'0'); let nreg : integer{} = 2; let mreg : integer = 2; let da : integer = UInt(ZAda); let sub_op : boolean = TRUE; let op1_unsigned : boolean = TRUE; let op2_unsigned : boolean = FALSE;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | Zm | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Zn | 0 | 1 | 1 | ZAda | ||||||
| u0 | u1 | M | N | S | |||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SME_MOP4) || !IsFeatureImplemented(FEAT_SME_I16I64) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 64; let n : integer = UInt('0'::Zn::'0'); let m : integer = UInt('1'::Zm::'0'); let nreg : integer{} = 1; let mreg : integer = 2; let da : integer = UInt(ZAda); let sub_op : boolean = TRUE; let op1_unsigned : boolean = TRUE; let op2_unsigned : boolean = FALSE;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | Zm | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Zn | 0 | 1 | 1 | ZAda | ||||||
| u0 | u1 | M | N | S | |||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SME_MOP4) || !IsFeatureImplemented(FEAT_SME_I16I64) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 64; let n : integer = UInt('0'::Zn::'0'); let m : integer = UInt('1'::Zm::'0'); let nreg : integer{} = 1; let mreg : integer = 1; let da : integer = UInt(ZAda); let sub_op : boolean = TRUE; let op1_unsigned : boolean = TRUE; let op2_unsigned : boolean = FALSE;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | Zm | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | Zn | 0 | 1 | 1 | ZAda | ||||||
| u0 | u1 | M | N | S | |||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SME_MOP4) || !IsFeatureImplemented(FEAT_SME_I16I64) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 64; let n : integer = UInt('0'::Zn::'0'); let m : integer = UInt('1'::Zm::'0'); let nreg : integer{} = 2; let mreg : integer = 1; let da : integer = UInt(ZAda); let sub_op : boolean = TRUE; let op1_unsigned : boolean = TRUE; let op2_unsigned : boolean = FALSE;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | Zm | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | Zn | 0 | 1 | 1 | ZAda | ||||||
| u0 | u1 | M | N | S | |||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SME_MOP4) || !IsFeatureImplemented(FEAT_SME_I16I64) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 64; let n : integer = UInt('0'::Zn::'0'); let m : integer = UInt('1'::Zm::'0'); let nreg : integer{} = 2; let mreg : integer = 2; let da : integer = UInt(ZAda); let sub_op : boolean = TRUE; let op1_unsigned : boolean = TRUE; let op2_unsigned : boolean = FALSE;
| <Zn> |
Is the name of the first source scalable vector register, registers in the range Z0-Z15, encoded as "Zn" times 2. |
| <Zm1> |
Is the name of the first scalable vector register of the second source multi-vector group, in the range Z16-Z31, encoded as "Zm" times 2 plus 16. |
| <Zm2> |
Is the name of the second scalable vector register of the second source multi-vector group, in the range Z16-Z31, encoded as "Zm" times 2 plus 17. |
| <Zm> |
Is the name of the second source scalable vector register, registers in the range Z16-Z31, encoded as "Zm" times 2 plus 16. |
| <Zn1> |
Is the name of the first scalable vector register of the first source multi-vector group, in the range Z0-Z15, encoded as "Zn" times 2. |
| <Zn2> |
Is the name of the second scalable vector register of the first source multi-vector group, in the range Z0-Z15, encoded as "Zn" times 2 plus 1. |
CheckStreamingSVEAndZAEnabled(); let VL : integer{} = CurrentVL(); let hvsize : integer{} = VL DIV 2; let dim : integer{} = hvsize DIV esize; let tilesize : integer{} = 4*dim*dim*esize; let op3 : bits(tilesize) = ZAtile{}(da, esize); var result : bits(tilesize); var prod : integer; for outprod = 0 to 3 do let row_hv : integer = outprod DIVRM 2; let col_hv : integer = outprod MOD 2; let row_base : integer = row_hv * dim; let col_base : integer = col_hv * dim; let op1 : bits(VL) = Z{}(n + (nreg-1)*col_hv); let op2 : bits(VL) = Z{}(m + (mreg-1)*row_hv); for row = 0 to dim-1 do for col = 0 to dim-1 do let row_idx : integer = row_base + row; let col_idx : integer = col_base + col; let tile_idx : integer = row_idx * dim * 2 + col_idx; var sum : bits(esize) = op3[tile_idx*:esize]; for k = 0 to 3 do let op1elt : bits(esize DIV 4) = op1[(4*row_idx + k)*:(esize DIV 4)]; let op2elt : bits(esize DIV 4) = op2[(4*col_idx + k)*:(esize DIV 4)]; let element1 : integer = (if op1_unsigned then UInt(op1elt) else SInt(op1elt)); let element2 : integer = (if op2_unsigned then UInt(op2elt) else SInt(op2elt)); prod = element1 * element2; if sub_op then prod = -prod; end; sum = sum + prod; end; result[tile_idx*:esize] = sum; end; end; end; ZAtile{tilesize}(da, esize) = result;
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
2026-03_rel 2026-03-26 20:48:11
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