UUNPK

Unpack and zero-extend multi-vector elements

This instruction unpacks and zero-extends elements from one or two source vectors, and writes the zero-extended values into double width elements of the two or four destination vectors. This instruction is unpredicated.

It has encodings from 2 classes: Two registers and Four registers

Two registers
(FEAT_SME2)

313029282726252423222120191817161514131211109876543210
11000001size100101111000ZnZd1
U

Encoding

UUNPK { <Zd1>.<T>-<Zd2>.<T> }, <Zn>.<Tb>

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME2) then EndOfDecode(Decode_UNDEF); end; if size == '00' then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8 << UInt(size); let n : integer = UInt(Zn); let d : integer = UInt(Zd::'0'); let nreg : integer{} = 2; let unsigned : boolean = TRUE;

Four registers
(FEAT_SME2)

313029282726252423222120191817161514131211109876543210
11000001size110101111000Zn0Zd01
U

Encoding

UUNPK { <Zd1>.<T>-<Zd4>.<T> }, { <Zn1>.<Tb>-<Zn2>.<Tb> }

Decode for this encoding

if !IsFeatureImplemented(FEAT_SME2) then EndOfDecode(Decode_UNDEF); end; if size == '00' then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8 << UInt(size); let n : integer = UInt(Zn::'0'); let d : integer = UInt(Zd::'00'); let nreg : integer{} = 4; let unsigned : boolean = TRUE;

Assembler Symbols

<Zd1>

For the "Two registers" variant: is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 2.

For the "Four registers" variant: is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 4.

<T>

Is the size specifier, encoded in size:

size <T>
00 RESERVED
01 H
10 S
11 D
<Zd2>

Is the name of the second scalable vector register of the destination multi-vector group, encoded as "Zd" times 2 plus 1.

<Zn>

Is the name of the source scalable vector register, encoded in the "Zn" field.

<Tb>

Is the size specifier, encoded in size:

size <Tb>
00 RESERVED
01 B
10 H
11 S
<Zd4>

Is the name of the fourth scalable vector register of the destination multi-vector group, encoded as "Zd" times 4 plus 3.

<Zn1>

Is the name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 2.

<Zn2>

Is the name of the second scalable vector register of the source multi-vector group, encoded as "Zn" times 2 plus 1.

Operation

CheckStreamingSVEEnabled(); let VL : integer{} = CurrentVL(); let elements : integer = VL DIV esize; let hsize : integer{} = esize DIV 2; let sreg : integer = nreg DIV 2; var results : array [[4]] of bits(VL); for r = 0 to sreg-1 do let operand : bits(VL) = Z{}(n+r); for i = 0 to 1 do for e = 0 to elements-1 do let element : bits(hsize) = operand[(i*elements + e)*:hsize]; results[[2*r+i]][e*:esize] = Extend{esize}(element, unsigned); end; end; end; for r = 0 to nreg-1 do Z{VL}(d+r) = results[[r]]; end;

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.


2026-03_rel 2026-03-26 20:48:11

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