While incrementing signed scalar less than or equal to scalar (predicate-as-counter)
This instruction generates a predicate for a group of two or four vectors that starting from the lowest numbered element of the group is true while the incrementing value of the first, signed scalar operand is less than or equal to the second scalar operand and false thereafter up to the highest numbered element of the group.
If the second scalar operand is equal to the maximum signed integer value, then a condition that includes an equality test can never fail and the result will be an all-true predicate.
The full width of the scalar operands is significant for the purposes of comparison, and the full width first operand is incremented by one for each destination predicate element, irrespective of the predicate result element size.
The predicate result is placed in the predicate destination register using the predicate-as-counter encoding. This instruction sets the First (N), None (Z), and !Last (C) condition flags based on the predicate result, and sets the V flag to zero.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | size | 1 | Rm | 0 | 1 | vl | 0 | 0 | 1 | Rn | 1 | 1 | PNd | |||||||||||
| U | lt | eq | |||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SME2) && !IsFeatureImplemented(FEAT_SVE2p1) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8 << UInt(size); let rsize : integer{} = 64; let n : integer = UInt(Rn); let m : integer = UInt(Rm); let d : integer = UInt('1'::PNd); let unsigned : boolean = FALSE; let invert : boolean = FALSE; let op : CmpOp = Cmp_LE; let width : integer = 2 << UInt(vl);
| <PNd> |
Is the name of the destination scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNd" field. |
| <T> |
Is the size specifier,
encoded in
|
| <Xn> |
Is the 64-bit name of the first source general-purpose register, encoded in the "Rn" field. |
| <Xm> |
Is the 64-bit name of the second source general-purpose register, encoded in the "Rm" field. |
| <vl> |
Is the vl specifier,
encoded in
|
if IsFeatureImplemented(FEAT_SVE2p1) then CheckSVEEnabled(); else CheckStreamingSVEEnabled(); end; let VL : integer{} = CurrentVL(); let PL : integer{} = VL DIV 8; let elements : integer = width * (VL DIV esize); var operand1 : bits(rsize) = X{}(n); let operand2 : bits(rsize) = X{}(m); var result : bits(PL); var last : boolean = TRUE; var count : integer = 0; let op2val : integer = if unsigned then UInt(operand2) else SInt(operand2); for e = 0 to elements-1 do let op1val : integer = if unsigned then UInt(operand1) else SInt(operand1); var cond : boolean; case op of when Cmp_LT => cond = (op1val < op2val); when Cmp_LE => cond = (op1val <= op2val); end; last = last && cond; if last then count = count + 1; end; operand1 = operand1 + 1; end; result = EncodePredCount{PL}(esize, elements, count, invert); PSTATE.[N,Z,C,V] = PredCountTest(elements, count, invert); P{PL}(d) = result;
2026-03_rel 2026-03-26 20:48:11
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