While free of read-after-write conflicts
This instruction checks two addresses for a conflict or overlap between address ranges of the form [addr,addr+VL÷8), where VL is the accessible vector length in bits, that could result in a loop-carried dependency through memory due to the use of these addresses by contiguous load and store instructions within the same iteration of a loop. Generate a predicate whose elements are true while the addresses cannot conflict within the same iteration, and false thereafter. This instruction sets the First (N), None (Z), and !Last (C) condition flags based on the predicate result, and sets the V flag to zero.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | size | 1 | Rm | 0 | 0 | 1 | 1 | 0 | 0 | Rn | 1 | Pd | ||||||||||||
| rw | |||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8 << UInt(size); let n : integer = UInt(Rn); let m : integer = UInt(Rm); let d : integer = UInt(Pd);
| <Pd> |
Is the name of the destination scalable predicate register, encoded in the "Pd" field. |
| <T> |
Is the size specifier,
encoded in
|
| <Xn> |
Is the 64-bit name of the first source general-purpose register, encoded in the "Rn" field. |
| <Xm> |
Is the 64-bit name of the second source general-purpose register, encoded in the "Rm" field. |
CheckSVEEnabled(); let VL : integer{} = CurrentVL(); let PL : integer{} = VL DIV 8; let elements : integer = VL DIV esize; let mask : bits(PL) = Ones{}; let src1 : bits(64) = X{}(n); let src2 : bits(64) = X{}(m); let operand1 : integer = UInt(src1); let operand2 : integer = UInt(src2); var result : bits(PL); let psize : integer{} = esize DIV 8; let diff : integer = Abs(operand2 - operand1) DIVRM (esize DIV 8); for e = 0 to elements-1 do if diff == 0 || e < diff then result[e*:psize] = ZeroExtend{psize}('1'); else result[e*:psize] = ZeroExtend{psize}('0'); end; end; PSTATE.[N,Z,C,V] = PredTest{PL}(mask, result, esize); P{PL}(d) = result;
2026-03_rel 2026-03-26 20:48:11
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