Add replicated single vector to multi-vector with multi-vector result
Add elements of the second source vector to the corresponding elements of the two or four first source vectors and destructively place the results in the corresponding elements of the two or four first source vectors.
This instruction is unpredicated.
It has encodings from 2 classes: Two registers and Four registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | size | 1 | 0 | Zm | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | Zdn | 0 |
if !HaveSME2() then UNDEFINED; constant integer esize = 8 << UInt(size); integer dn = UInt(Zdn:'0'); integer m = UInt('0':Zm); constant integer nreg = 2;
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | size | 1 | 0 | Zm | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | Zdn | 0 | 0 |
if !HaveSME2() then UNDEFINED; constant integer esize = 8 << UInt(size); integer dn = UInt(Zdn:'00'); integer m = UInt('0':Zm); constant integer nreg = 4;
<T> |
Is the size specifier,
encoded in
|
<Zdn4> |
Is the name of the fourth scalable vector register of the destination and first source multi-vector group, encoded as "Zdn" times 4 plus 3. |
<Zdn2> |
Is the name of the second scalable vector register of the destination and first source multi-vector group, encoded as "Zdn" times 2 plus 1. |
<Zm> |
Is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field. |
CheckStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV esize; array [0..3] of bits(VL) results; for r = 0 to nreg-1 bits(VL) operand1 = Z[dn+r, VL]; bits(VL) operand2 = Z[m, VL]; for e = 0 to elements-1 bits(esize) element1 = Elem[operand1, e, esize]; bits(esize) element2 = Elem[operand2, e, esize]; Elem[results[r], e, esize] = element1 + element2; for r = 0 to nreg-1 Z[dn+r, VL] = results[r];
If PSTATE.DIT is 1:
Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46
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