Add narrow high part (top)
Add each vector element of the first source vector to the corresponding vector element of the second source vector, and place the most significant half of the result in the odd-numbered half-width destination elements, leaving the even-numbered elements unchanged. This instruction is unpredicated.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | size | 1 | Zm | 0 | 1 | 1 | 0 | 0 | 1 | Zn | Zd | |||||||||||||
| S | R | T | |||||||||||||||||||||||||||||
if !HaveSVE2() && !HaveSME() then UNDEFINED; if size == '00' then UNDEFINED; constant integer esize = 8 << UInt(size); integer n = UInt(Zn); integer m = UInt(Zm); integer d = UInt(Zd);
| <Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field. |
| <T> |
Is the size specifier,
encoded in
|
| <Zn> |
Is the name of the first source scalable vector register, encoded in the "Zn" field. |
| <Tb> |
Is the size specifier,
encoded in
|
| <Zm> |
Is the name of the second source scalable vector register, encoded in the "Zm" field. |
CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV esize; bits(VL) operand1 = Z[n, VL]; bits(VL) operand2 = Z[m, VL]; bits(VL) result = Z[d, VL]; constant integer halfesize = esize DIV 2; for e = 0 to elements-1 integer element1 = UInt(Elem[operand1, e, esize]); integer element2 = UInt(Elem[operand2, e, esize]); integer res = (element1 + element2) >> halfesize; Elem[result, 2*e + 1, halfesize] = res<halfesize-1:0>; Z[d, VL] = result;
If FEAT_SVE2 is implemented or FEAT_SME is implemented, then if PSTATE.DIT is 1:
Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46
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