Add multiple of vector register size to scalar register
Add the current vector register size in bytes multiplied by an immediate in the range -32 to 31 to the 64-bit source general-purpose register or current stack pointer, and place the result in the 64-bit destination general-purpose register or current stack pointer.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | Rn | 0 | 1 | 0 | 1 | 0 | imm6 | Rd | |||||||||||||
if !HaveSVE() && !HaveSME() then UNDEFINED; integer n = UInt(Rn); integer d = UInt(Rd); integer imm = SInt(imm6);
| <Xd|SP> |
Is the 64-bit name of the destination general-purpose register or stack pointer, encoded in the "Rd" field. |
| <Xn|SP> |
Is the 64-bit name of the source general-purpose register or stack pointer, encoded in the "Rn" field. |
| <imm> |
Is the signed immediate operand, in the range -32 to 31, encoded in the "imm6" field. |
CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; bits(64) operand1 = if n == 31 then SP[] else X[n, 64]; bits(64) result = operand1 + (imm * (VL DIV 8)); if d == 31 then SP[] = result; else X[d, 64] = result;
If FEAT_SVE2 is implemented or FEAT_SME is implemented, then if PSTATE.DIT is 1:
Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46
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