BFloat16 floating-point matrix multiply-accumulate into 2x2 matrix.
If FEAT_EBF16 is not implemented or FPCR.EBF is 0, this instruction:
If FEAT_EBF16 is implemented and FPCR.EBF is 1, then this instruction:
Irrespective of FEAT_EBF16 and FPCR.EBF, this instruction:
ID_AA64ISAR1_EL1.BF16 indicates whether this instruction is supported.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | Rm | 1 | 1 | 1 | 0 | 1 | 1 | Rn | Rd | ||||||||||||
Q | U | size | opcode |
if !IsFeatureImplemented(FEAT_BF16) then UNDEFINED; integer n = UInt(Rn); integer m = UInt(Rm); integer d = UInt(Rd);
<Vd> |
Is the name of the SIMD&FP third source and destination register, encoded in the "Rd" field. |
<Vn> |
Is the name of the first SIMD&FP source register, encoded in the "Rn" field. |
<Vm> |
Is the name of the second SIMD&FP source register, encoded in the "Rm" field. |
CheckFPAdvSIMDEnabled64(); bits(128) op1 = V[n, 128]; bits(128) op2 = V[m, 128]; bits(128) acc = V[d, 128]; V[d, 128] = BFMatMulAdd(acc, op1, op2, FPCR);
Arm expects that the BFMMLA instruction will deliver a peak BFloat16 multiply throughput that is at least as high as can be achieved using two BFDOT (vector) instructions, with a goal that it should have significantly higher throughput.
Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46
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