BRKB

Break before first true condition

Sets destination predicate elements up to but not including the first active and true source element to true, then sets subsequent elements to false. Inactive elements in the destination predicate register remain unmodified or are set to zero, depending on whether merging or zeroing predication is selected. Does not set the condition flags.

313029282726252423222120191817161514131211109876543210
001001011001000001Pg0PnMPd
BS

BRKB <Pd>.B, <Pg>/<ZM>, <Pn>.B

if !HaveSVE() && !HaveSME() then UNDEFINED; constant integer esize = 8; integer g = UInt(Pg); integer n = UInt(Pn); integer d = UInt(Pd); boolean merging = (M == '1'); boolean setflags = FALSE;

Assembler Symbols

<Pd>

Is the name of the destination scalable predicate register, encoded in the "Pd" field.

<Pg>

Is the name of the governing scalable predicate register, encoded in the "Pg" field.

<ZM>

Is the predication qualifier, encoded in M:

M <ZM>
0 Z
1 M
<Pn>

Is the name of the source scalable predicate register, encoded in the "Pn" field.

Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; bits(PL) mask = P[g, PL]; bits(PL) operand = P[n, PL]; bits(PL) operand2 = P[d, PL]; boolean break = FALSE; bits(PL) result; constant integer psize = esize DIV 8; for e = 0 to elements-1 boolean element = ActivePredicateElement(operand, e, esize); if ActivePredicateElement(mask, e, esize) then break = break || element; bit pbit = if !break then '1' else '0'; Elem[result, e, psize] = ZeroExtend(pbit, psize); elsif merging then bit pbit = PredicateElement(operand2, e, esize); Elem[result, e, psize] = ZeroExtend(pbit, psize); else Elem[result, e, psize] = ZeroExtend('0', psize); if setflags then PSTATE.<N,Z,C,V> = PredTest(mask, result, esize); P[d, PL] = result;


Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46

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