CDOT (vectors)

Complex integer dot product

The complex integer dot product instructions delimit the source vectors into pairs of 8-bit or 16-bit signed integer complex numbers. Within each pair, the complex numbers in the first source vector are multiplied by the corresponding complex numbers in the second source vector and the resulting wide real or wide imaginary part of the product is accumulated into a 32-bit or 64-bit destination vector element which overlaps all four of the elements that comprise a pair of complex number values in the first source vector.

As a result each instruction implicitly deinterleaves the real and imaginary components of their complex number inputs, so that the destination vector accumulates 4×wide real sums or 4×wide imaginary sums.

The complex numbers in the second source vector are rotated by 0, 90, 180 or 270 degrees in the direction from the positive real axis towards the positive imaginary axis, when considered in polar representation, by performing the following transformations prior to the dot product operations:

Each complex number is represented in a vector register as an even/odd pair of elements with the real part in the even-numbered element and the imaginary part in the odd-numbered element.

313029282726252423222120191817161514131211109876543210
01000100size0Zm0001rotZnZda

CDOT <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>, <const>

if !HaveSVE2() && !HaveSME() then UNDEFINED; if size IN {'0x'} then UNDEFINED; constant integer esize = 8 << UInt(size); integer n = UInt(Zn); integer m = UInt(Zm); integer da = UInt(Zda); integer sel_a = UInt(rot<0>); integer sel_b = UInt(NOT(rot<0>)); boolean sub_i = (rot<0> == rot<1>);

Assembler Symbols

<Zda>

Is the name of the third source and destination scalable vector register, encoded in the "Zda" field.

<T>

Is the size specifier, encoded in size<0>:

size<0> <T>
0 S
1 D
<Zn>

Is the name of the first source scalable vector register, encoded in the "Zn" field.

<Tb>

Is the size specifier, encoded in size<0>:

size<0> <Tb>
0 B
1 H
<Zm>

Is the name of the second source scalable vector register, encoded in the "Zm" field.

<const>

Is the const specifier, encoded in rot:

rot <const>
00 #0
01 #90
10 #180
11 #270

Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV esize; bits(VL) operand1 = Z[n, VL]; bits(VL) operand2 = Z[m, VL]; bits(VL) operand3 = Z[da, VL]; bits(VL) result; for e = 0 to elements-1 bits(esize) res = Elem[operand3, e, esize]; for i = 0 to 1 integer elt1_r = SInt(Elem[operand1, 4 * e + 2 * i + 0, esize DIV 4]); integer elt1_i = SInt(Elem[operand1, 4 * e + 2 * i + 1, esize DIV 4]); integer elt2_a = SInt(Elem[operand2, 4 * e + 2 * i + sel_a, esize DIV 4]); integer elt2_b = SInt(Elem[operand2, 4 * e + 2 * i + sel_b, esize DIV 4]); if sub_i then res = (res + (elt1_r * elt2_a)) - (elt1_i * elt2_b); else res = res + (elt1_r * elt2_a) + (elt1_i * elt2_b); Elem[result, e, esize] = res; Z[da, VL] = result;

Operational information

This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX instruction must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is unpredictable:


Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46

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