Conditionally extract last element to SIMD&FP scalar register
From the source vector register extract the last active element, and then zero-extend that element to destructively place in the destination and first source SIMD & floating-point scalar register. If there are no active elements then destructively zero-extend the least significant element-size bits of the destination and first source SIMD & floating-point scalar register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | size | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | Pg | Zm | Vdn | |||||||||||
| B | |||||||||||||||||||||||||||||||
if !HaveSVE() && !HaveSME() then UNDEFINED; constant integer esize = 8 << UInt(size); integer g = UInt(Pg); integer dn = UInt(Vdn); integer m = UInt(Zm); boolean isBefore = TRUE;
| <V> |
Is a width specifier,
encoded in
|
| <dn> |
Is the number [0-31] of the source and destination SIMD&FP register, encoded in the "Vdn" field. |
| <Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
| <Zm> |
Is the name of the source scalable vector register, encoded in the "Zm" field. |
| <T> |
Is the size specifier,
encoded in
|
CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; bits(PL) mask = P[g, PL]; bits(esize) operand1 = V[dn, esize]; bits(VL) operand2 = Z[m, VL]; bits(esize) result; integer last = LastActiveElement(mask, esize); if last < 0 then result = ZeroExtend(operand1, esize); else if !isBefore then last = last + 1; if last >= elements then last = 0; result = Elem[operand2, last, esize]; V[dn, esize] = result;
Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46
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