Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
It has encodings from 2 classes: Scalar and Vector
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| 0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | Rn | Rd | ||||||||
| U | size | opcode | |||||||||||||||||||||||||||||
integer d = UInt(Rd); integer n = UInt(Rn); if size != '11' then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer datasize = esize; integer elements = 1; CompareOp comparison = CompareOp_LT;
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| 0 | Q | 0 | 0 | 1 | 1 | 1 | 0 | size | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | Rn | Rd | |||||||||
| U | opcode | ||||||||||||||||||||||||||||||
integer d = UInt(Rd); integer n = UInt(Rn); if size:Q == '110' then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer datasize = 64 << UInt(Q); integer elements = datasize DIV esize; CompareOp comparison = CompareOp_LT;
| <d> |
Is the number of the SIMD&FP destination register, encoded in the "Rd" field. |
| <n> |
Is the number of the SIMD&FP source register, encoded in the "Rn" field. |
| <Vd> |
Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
| <T> |
Is an arrangement specifier,
encoded in
|
| <Vn> |
Is the name of the SIMD&FP source register, encoded in the "Rn" field. |
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n, datasize]; bits(datasize) result; integer element; boolean test_passed; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); case comparison of when CompareOp_GT test_passed = element > 0; when CompareOp_GE test_passed = element >= 0; when CompareOp_EQ test_passed = element == 0; when CompareOp_LE test_passed = element <= 0; when CompareOp_LT test_passed = element < 0; Elem[result, e, esize] = if test_passed then Ones(esize) else Zeros(esize); V[d, datasize] = result;
If PSTATE.DIT is 1:
Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46
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