CNTB, CNTD, CNTH, CNTW

Set scalar to multiple of predicate constraint element count

Determines the number of active elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then places the result in the scalar destination.

The named predicate constraint limits the number of active elements in a single predicate to:

Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.

It has encodings from 4 classes: Byte , Doubleword , Halfword and Word

Byte

313029282726252423222120191817161514131211109876543210
000001000010imm4111000patternRd
size<1>size<0>

CNTB <Xd>{, <pattern>{, MUL #<imm>}}

if !HaveSVE() && !HaveSME() then UNDEFINED; constant integer esize = 8; integer d = UInt(Rd); bits(5) pat = pattern; integer imm = UInt(imm4) + 1;

Doubleword

313029282726252423222120191817161514131211109876543210
000001001110imm4111000patternRd
size<1>size<0>

CNTD <Xd>{, <pattern>{, MUL #<imm>}}

if !HaveSVE() && !HaveSME() then UNDEFINED; constant integer esize = 64; integer d = UInt(Rd); bits(5) pat = pattern; integer imm = UInt(imm4) + 1;

Halfword

313029282726252423222120191817161514131211109876543210
000001000110imm4111000patternRd
size<1>size<0>

CNTH <Xd>{, <pattern>{, MUL #<imm>}}

if !HaveSVE() && !HaveSME() then UNDEFINED; constant integer esize = 16; integer d = UInt(Rd); bits(5) pat = pattern; integer imm = UInt(imm4) + 1;

Word

313029282726252423222120191817161514131211109876543210
000001001010imm4111000patternRd
size<1>size<0>

CNTW <Xd>{, <pattern>{, MUL #<imm>}}

if !HaveSVE() && !HaveSME() then UNDEFINED; constant integer esize = 32; integer d = UInt(Rd); bits(5) pat = pattern; integer imm = UInt(imm4) + 1;

Assembler Symbols

<Xd>

Is the 64-bit name of the destination general-purpose register, encoded in the "Rd" field.

<pattern>

Is the optional pattern specifier, defaulting to ALL, encoded in pattern:

pattern <pattern>
00000 POW2
00001 VL1
00010 VL2
00011 VL3
00100 VL4
00101 VL5
00110 VL6
00111 VL7
01000 VL8
01001 VL16
01010 VL32
01011 VL64
01100 VL128
01101 VL256
0111x #uimm5
101x1 #uimm5
10110 #uimm5
1x0x1 #uimm5
1x010 #uimm5
1xx00 #uimm5
11101 MUL4
11110 MUL3
11111 ALL
<imm>

Is the immediate multiplier, in the range 1 to 16, defaulting to 1, encoded in the "imm4" field.

Operation

CheckSVEEnabled(); integer count = DecodePredCount(pat, esize); X[d, 64] = (count * imm)<63:0>;

Operational information

If FEAT_SVE2 is implemented or FEAT_SME is implemented, then if PSTATE.DIT is 1:


Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46

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