Broadcast indexed element within each quadword vector segment (unpredicated)
Unconditionally broadcast the indexed element within each 128-bit source vector segment to all elements of the corresponding destination vector segment. This instruction is unpredicated.
The immediate element index is in the range of 0 to 15 (bytes), 7 (halfwords), 3 (words) or 1 (doublewords).
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | i1 | tsz | 0 | 0 | 1 | 0 | 0 | 1 | Zn | Zd | |||||||||||
if !HaveSVE2p1() && !HaveSME2p1() then UNDEFINED; if tsz == '0000' then UNDEFINED; constant integer lsb = LowestSetBit(tsz); constant integer esize = 8 << lsb; constant bits(5) imm = i1:tsz; constant integer index = UInt(imm<4:(lsb+1)>); integer n = UInt(Zn); integer d = UInt(Zd);
| <Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field. |
| <T> |
Is the size specifier,
encoded in
|
| <Zn> |
Is the name of the source scalable vector register, encoded in the "Zn" field. |
| <imm> |
Is the immediate index, in the range 0 to one less than the number of elements in 128 bits, encoded in "i1:tsz". |
CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer segments = VL DIV 128; constant integer elements = 128 DIV esize; bits(VL) operand = Z[n, VL]; bits(VL) result; bits(esize) element; for s = 0 to segments-1 element = Elem[operand, s * elements + index, esize]; Elem[result, s, 128] = Replicate(element, 128 DIV esize); Z[d, VL] = result;
If PSTATE.DIT is 1:
Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46
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