Multi-vector floating-point convert from 8-bit floating-point to deinterleaved half-precision
Convert each 8-bit floating-point element of the source vector to half-precision while downscaling the value, and place the deinterleaved results in the corresponding 16-bit elements of the destination vectors. F1CVTL scales the values by 2-UInt(FPMR.LSCALE[3:0]). F2CVTL scales the values by 2-UInt(FPMR.LSCALE2[3:0]). The 8-bit floating-point encoding format for F1CVTL is selected by FPMR.F8S1. The 8-bit floating-point encoding format for F2CVTL is selected by FPMR.F8S2.
This instruction is unpredicated.
It has encodings from 2 classes: F1CVTL and F2CVTL
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| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | Zn | Zd | 1 | |||||||
| L | |||||||||||||||||||||||||||||||
if !HaveSME2() || !IsFeatureImplemented(FEAT_FP8) then UNDEFINED; integer n = UInt(Zn); integer d = UInt(Zd: '0'); boolean issrc2 = FALSE;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | Zn | Zd | 1 | |||||||
| L | |||||||||||||||||||||||||||||||
if !HaveSME2() || !IsFeatureImplemented(FEAT_FP8) then UNDEFINED; integer n = UInt(Zn); integer d = UInt(Zd: '0'); boolean issrc2 = TRUE;
| <Zd1> |
Is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 2. |
| <Zd2> |
Is the name of the second scalable vector register of the destination multi-vector group, encoded as "Zd" times 2 plus 1. |
| <Zn> |
Is the name of the source scalable vector register, encoded in the "Zn" field. |
CheckFPMREnabled(); CheckStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer pairs = VL DIV 16; bits(VL) operand = Z[n, VL]; bits(VL) result1; bits(VL) result2; for p = 0 to pairs-1 bits(8) element1 = Elem[operand, 2*p + 0, 8]; bits(8) element2 = Elem[operand, 2*p + 1, 8]; Elem[result1, p, 16] = FP8ConvertFP(element1, issrc2, FPCR, FPMR); Elem[result2, p, 16] = FP8ConvertFP(element2, issrc2, FPCR, FPMR); Z[d+0, VL] = result1; Z[d+1, VL] = result2;
Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46
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