FADDA

Floating-point add a SIMD&FP scalar source and all active lanes of the vector source and place the result destructively in the SIMD&FP scalar source register. Vector elements are processed strictly in order from low to high, with the scalar source providing the initial value. Inactive elements in the source vector are ignored.

This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.

if !HaveSVE() then UNDEFINED; if size == '00' then UNDEFINED; constant integer esize = 8 << UInt(size); integer g = UInt(Pg); integer dn = UInt(Vdn); integer m = UInt(Zm);

Assembler Symbols

<V>

Is a width specifier, encoded in size:

size	<V>
00	RESERVED
01	H
10	S
11	D

<dn>	Is the number [0-31] of the source and destination SIMD&FP register, encoded in the "Vdn" field.

<Pg>	Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Zm>	Is the name of the source scalable vector register, encoded in the "Zm" field.

<T>

Is the size specifier, encoded in size:

size	<T>
00	RESERVED
01	H
10	S
11	D

Operation

CheckNonStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; bits(PL) mask = P[g, PL]; bits(esize) operand1 = V[dn, esize]; bits(VL) operand2 = if AnyActiveElement(mask, esize) then Z[m, VL] else Zeros(VL); bits(esize) result = operand1; for e = 0 to elements-1 if ActivePredicateElement(mask, e, esize) then bits(esize) element = Elem[operand2, e, esize]; result = FPAdd(result, element, FPCR); V[dn, esize] = result;

Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	1	1	0	0	1	0	1	size		0	1	1	0	0	0	0	0	1	Pg			Zm					Vdn

FADDA

FADDA <V><dn>, <Pg>, <V><dn>, <Zm>.<T>

Assembler Symbols

Operation