Floating-point add pairwise
Add pairs of adjacent floating-point elements within each source vector, and interleave the results from corresponding lanes. The interleaved result values are destructively placed in the first source vector.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | size | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | Pg | Zm | Zdn | |||||||||||
if !HaveSVE2() && !HaveSME() then UNDEFINED; if size == '00' then UNDEFINED; constant integer esize = 8 << UInt(size); integer g = UInt(Pg); integer m = UInt(Zm); integer dn = UInt(Zdn);
| <Zdn> |
Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field. |
| <T> |
Is the size specifier,
encoded in
|
| <Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
| <Zm> |
Is the name of the second source scalable vector register, encoded in the "Zm" field. |
CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; bits(PL) mask = P[g, PL]; bits(VL) operand1 = Z[dn, VL]; bits(VL) operand2 = if AnyActiveElement(mask, esize) then Z[m, VL] else Zeros(VL); bits(VL) result = Z[dn, VL]; bits(esize) element1; bits(esize) element2; for e = 0 to elements-1 if ActivePredicateElement(mask, e, esize) then if IsEven(e) then element1 = Elem[operand1, e + 0, esize]; element2 = Elem[operand1, e + 1, esize]; else element1 = Elem[operand2, e - 1, esize]; element2 = Elem[operand2, e + 0, esize]; Elem[result, e, esize] = FPAdd(element1, element2, FPCR); Z[dn, VL] = result;
This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX instruction must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is unpredictable:
Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46
Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.