FCPY

Copy a floating-point immediate into each active element in the destination vector. Inactive elements in the destination vector register remain unmodified.

if !HaveSVE() && !HaveSME() then UNDEFINED; if size == '00' then UNDEFINED; constant integer esize = 8 << UInt(size); integer g = UInt(Pg); integer d = UInt(Zd); bits(esize) imm = VFPExpandImm(imm8, esize);

Assembler Symbols

<Zd>	Is the name of the destination scalable vector register, encoded in the "Zd" field.

<T>

Is the size specifier, encoded in size:

size	<T>
00	RESERVED
01	H
10	S
11	D

<Pg>	Is the name of the governing scalable predicate register, encoded in the "Pg" field.

<const>

Is a floating-point immediate value expressible as ±n÷16×2^r, where n and r are integers such that 16 ≤ n ≤ 31 and -3 ≤ r ≤ 4, i.e. a normalized binary floating-point encoding with 1 sign bit, 3-bit exponent, and 4-bit fractional part, encoded in the "imm8" field.

Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; bits(PL) mask = P[g, PL]; bits(VL) result = Z[d, VL]; for e = 0 to elements-1 if ActivePredicateElement(mask, e, esize) then Elem[result, e, esize] = imm; Z[d, VL] = result;

Operational information

This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX instruction must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is unpredictable:

The MOVPRFX instruction must be unpredicated, or be predicated using the same governing predicate register and source element size as this instruction.
The MOVPRFX instruction must specify the same destination register as this instruction.
The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.

Internal version only: aarchmrs v2023-12_rel, pseudocode v2023-12_rel, sve v2023-12_rel ; Build timestamp: 2023-12-15T16:46

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	0	0	0	1	0	1	size		0	1	Pg				1	1	0	imm8								Zd

FCPY

FCPY <Zd>.<T>, <Pg>/M, #<const>

Assembler Symbols

Operation

Operational information